Binary digital pager having an eight function code read-out

• US 4,160,240 A
• Filed: 01/13/1978
• Issued: 07/03/1979
• Est. Priority Date: 01/13/1978
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Partipilo, Phillip
• Primary Examiner(s): Yusko, Donald J.
• Application Number:
  US05/869,394
• Time in Patent Office: 536 Days
• Field of Search: 340/311, 340/164 R, 340/167 R, 340/146.2, 340/146.1 BA, 325/464, 325/455, 325/392, 325/55, 325/64, 240/146.1 C
• US Class Current: 340/7.32
• CPC Class Codes: G08B 5/224 Paging receivers with visible signalling details
• CPC Class Codes: G08B 5/227 with call or message storage means
• CPC Class Codes: H04W 88/026 using digital address codes

Abstract

A read-out of eight distinct function codes is obtained in a pager or similar device having a single two-word address code plug by creating a second, but dependent, address within the pager and transmitting one of eight possible variants of the two words of the two address codes and their complements. Two code plugs may also be used to provide two addresses with four function codes associated with each. Upon receipt of a coded address, the user is alerted, and the function code is stored in a write-over memory, available to be read-out on command unitl a new code is received. The memory can also be erased manually as desired. Display segments are scanned in sequence to conserve power, and a status check of the segments is provided at each power turn-on. Power status indication is also provided, at turn-on and at "read" command, utilizing both audio alert channels and the visual display elements.

Claims

1. In a communications device for responding to a predetermined two-word binary address code within a stream of received data bits, logic circuitry for providing multiple function code displays comprising in combination;

first register means for sampling and temporarily retaining the received data bits;

storage means for permanently retaining binary address code data;

first circuit means coupled to the storage means for receiving the address code data and deriving therefrom the predetermined two-word address code;

second circuit means coupled to the storage means for receiving the address code data and deriving therefrom an address code related to the predetermined address code;

first comparator means for comparing the received data bits and the bits of the predetermined address code and for providing a first output signal indicative of substantial agreement therebetween;

second comparator means for comparing the received data bits and the bits of the address code related to the predetermined address code and for providing a second output signal indicative of substantial agreement therebetween;

indicator means for providing different indications in response to the first and second output signals.

2. A communications device in accordance with claim 1 and wherein the first comparator means provides a different output signal indicative of substantial agreement between the bits of the received data and the bits of the complements of at least one of the words of the predetermined address code, wherein the second comparator means provides still a different output signal indicative of substantial agreement between the bits of the received data and the bits of the complements of at least one of the words of the address code related to the predetermined address code, and wherein the indicator means provides a different indication in response to each said output signal.

3. A communications device in accordance with claim 1 wherein the indicator means is a visual display.

4. A communications device in accordance with claim 1 wherein the indicator means includes an array of light emitting diodes, and the different indications are numerical displays.

5. In a communications device for responding to a predetermined two-word binary address code within a stream of received data bits, logic circuitry for providing multiple function code displays comprising in combination:

first register means for sampling and retaining the received data bits;

storage means for retaining binary address code data;

second register means coupled to the storage means for receiving the binary address code data and deriving therefrom the predetermined binary address code;

third register means coupled to the storage means for receiving the binary address code data and deriving therefrom a binary address code related to the predetermined binary address code;

first correlating means for comparing output bits from the first register means with the bits of the first word from the second register means and providing a first output signal in response to a first predetermined number of correlations, and a second output signal in response to a second predetermined number of correlations;

first timing means for providing a first time period substantially equal to the transmission time of one address word in response to either the first or second output signals from the first correlating means, and a second time period subsequent to the first time period and substantially shorter than the first time period, the first correlating means comparing output bits from the first register means with the bits of the second word in the second register means only during the second time period and providing a third output signal in response to the first predetermined number of correlations and a fourth output signal in response to the second predetermined number of correlations;

first logic circuitry for recognizing combinations of the four possible output signals from the first correlating means;

second correlating means for comparing output bits from the first register means with the bits of the first work in the third register means and providing a fifth output signal in response to the first predetermined number of correlations, and a sixth output signal in response to the second predetermined number of correlations;

second timing means for providing the first period in response to either output signal from the second correlating means and for providing the second and subsequent time period, the second correlating output means comparing output bits from the first register means with the bits of the second word in the third register means only during the second time period and providing a seventh output signal in response to the first predetermined number of correlations and an eighth output signal in response to the second predetermined number of correlations;

second logic circuitry for recognizing combinations of the four possible output signals from the second correlating means; and

indicator means coupled to the first and second logic circuitry for providing one of eight distinct indications in response to each one of the eight possible output signals.

6. A communications device in accordance with claim 5 wherein the second and third register means each include a multiplex control gate, a reference register and a parity tree and the third register means further includes means for altering at least one of the bits received from the storage means.

7. A communications device in accordance with claim 6 wherein the means for altering the at least one received bit changes the said bit into the complement of said bit.

8. A communications device in accordance with claim 5 wherein the indicator means includes a visual display.

9. A communications device in accordance with claim 8 wherein the eight distinct indications are represented by numerical symbols.

10. A communications device in accordance with claim 8 wherein the visual display comprises a 7-segment light-emitting-diode display.

11. A communications device in accordance with claim 10 and further including scanning means for scanning the display elements in sequence for power conservation.

12. A communications device in accordance with claim 8 and further including third logic circuitry coupled to the indicator means for enabling all portions of the visual display for a brief period following power turn-on.

13. A communications device in accordance with claim 5 and further including circuitry coupled to the first and second correlating means for providing an audible indication in response to any of the possible output signals.

14. A communications device in accordance with claim 5 wherein the indicator means includes memory means for storing information corresponding to an output signal from one of the correlating means until another output signal is provided or until the stored information is manually erased.

15. A communications device in accordance with claim 5 and further including fourth logic circuitry for providing an indication of power source status.

16. A communications device in accordance with claim 15 and further including circuitry for providing audible indications, and wherein a first audible signal is provided at power turn-on when the power level is satisfactory and a second and distinct audible signal is provided if said level is unacceptable.

17. A communications device in accordance with claim 16 and further including circuitry coupled to the indicator means for causing a perceptible change in any displayed indication whenever the power source level is unacceptable.

18. A communications device in accordance with claim 17 and wherein the circuitry coupled to the indicator means includes a very low frequency oscillator and means for controlling the indicator at the signal rate of the oscillator.