Electronic display apparatus

• US 4,161,728 A
• Filed: 09/01/1977
• Issued: 07/17/1979
• Est. Priority Date: 09/06/1976
• Status: Expired due to Term

• Current Assignee: Plessey Semiconductors Limited (Plessey Group Holdings Ltd.)
• Original Assignee: General Electric (Shanghai) Co., Ltd. (GE Aerospace)
• Inventors: Insam, Edward F.
• Primary Examiner(s): Trafton, David L.
• Application Number:
  US05/829,710
• Time in Patent Office: 684 Days
• Field of Search: 340/324 AD, 340/337 A, 340/152 R, 358/85, 358/263, 358/903, 364/514, 179/2 TV
• US Class Current: 345/467
• CPC Class Codes: G09G 5/222 Control of the character-code memory
• CPC Class Codes: H04N 5/9207 for teletext
• CPC Class Codes: H04N 7/0882 for the transmission of character code signals, e.g. for teletext circuits for the digital non-picture data signal H04N7/035

Abstract

In a television receiver there are provided means for decoding and displaying data received in coded form either on a television carrier signal during field blanking periods or over a telephone line, the decoding means and the display means being interconnected by way of multiconductor data and address highways or buses. Data storage and data processing means, and also other data input means may be connected to these highways.

Claims

1. Apparatus for the display of information comprising a television-type display, character generator means for generating video signal elements for said display in response to data signals representing characters and symbols to be displayed, at least one receiver means for receiving and decoding coded signals including coded data signals, data storage means, a multiconductor bus arrangement over which data signals are transferred in parallel mode between said receiver means, said storage means and said character generator means, and a multiconductor address bus arrangement to which address signals are applied in parallel mode to control the transfer of said data signals on said data but to the required destination.

2. Apparatus in accordance with claim 1 including a microprocessor and means to connect said microprocessor to said multiconductor data bus and said multiconductor address bus.

3. Apparatus in accordance with claim 1 wherein connection means are provided along each bus for the releasable connection of at least said receiver means and said data storage means.

4. Apparatus in accordance with claim 3 wherein the connection means are socket connectors permanently connected to each said bus.

5. Apparatus in accordance with claim 1 wherein there are provided at least two data storage means each releasably connected to said data bus and to said address bus.