Inverter ripple regulator

• US 4,161,771 A
• Filed: 07/25/1977
• Issued: 07/17/1979
• Est. Priority Date: 07/25/1977
• Status: Expired due to Term

• Current Assignee: Gulton Industries, Inc.
• Original Assignee: Gulton Industries, Inc.
• Inventors: Bates, James W.
• Primary Examiner(s): Shoop, William M.
• Application Number:
  US05/818,350
• Time in Patent Office: 722 Days
• Field of Search: 307/82, 363/43, 363/65, 363/71, 363/72, 363/95-97, 363/101
• US Class Current: 363/43
• CPC Class Codes: G05F 1/62 using bucking or boosting dc sources
• CPC Class Codes: H02M 1/14 Arrangements for reducing ripples from dc input or output

Abstract

A sinusoidal-like output is obtained from a source of DC by adding the outputs of two or more DC to AC inverters, producing flat-topped pules combining to provide a normally near ideal stepped sinusoidal-like waveform, with the output of a buck-boost circuit which produces bucking or boosting outputs of one polarity or another when voltage regulation is called for or a zero output when no regulation is called for. The operation of the buck-boost circuit preferably is controlled by a circuit which responds to the combinations of polarities of voltages obtained at two signal tap-off points of a bridge circuit including first and second input terminals between which terminals and a common terminal are connected in opposite phase a low power, low amplitude ideal sinusoidal reference signal and a proportionate part of the filtered combined outputs of the inverter and buck-boost circuits, the magnitude of the combined signal output at said second terminal being selected to normally match that of said reference signal at said second output terminal. A series circuit of a number of impedance means are connected between said signal input terminals, and said tap-off points are made at points along said series circuit of impedance means which are symmetrically related with respect to an intermediate impedance point therebetween which is at zero potential with respect to said common terminal when the reference signal and combined signal output at said first and second input terminals are of equal value.

Claims

1. A converter circuit for providing a regulated sinusoidal-like output voltage under varying load current conditions from DC, said converter circuit comprising, in combination:

DC voltage source means;

a source of a reference signal having the desired sinusoidal-like waveform;

inverter circuit means energized by said DC voltage source means for providing an output which at least roughly approximates a desired sinusoidal-like output, a buck-boost circuit having a first output condition where the output thereof is a first finite signal of one polarity which is a fraction of the maximum amplitude of said output, a second output condition where the output thereof is a second finite signal of the same amplitude but opposite polarity to said first finite signal, and a third output condition where the output thereof is zero;

means for adding the output of said buck-boost circuit to the output of said inverter circuit means to produce an overall combined output;

comparator means for comparing the output of said reference signal source and at least a part of said overall combined output of said inverter circuit and buck-boost circuits which has an amplitude comparable to said reference signal; and

control means responsive repeatedly over each half cycle to said comparator means for operating said buck-boost circuit into one of said output conditions for a desired period which brings said overall resultant output toward the instantaneous level of the desired sinusoidal output.

2. The converter circuit of claim 1 wherein the value of said finite signals of said one and opposite polarities is such as to cause said overall combined output of said inverter circuit means and buck-boost circuit to alternate on opposite sides of the desired sinusoidal-like output to provide a relatively high frequency ripple upon an envelope following the waveform of the desired output.

3. The converter circuit of claim 1 wherein said comparator circuit has output terminal means, and means for providing (a) a first output signal condition on said output terminal means when the instantaneous value of the reference signal is above said overall combined output compared therewith, (b) a second output signal condition on said output terminal means when the instantaneous value of said reference signal is below said overall combined output compared therewith, and (c) a third output signal condition on said output terminal means when the instantaneous value of said reference signal is equal to said overall combined output compared therewith, and said control means comprising means for operating said buck-boost circuit respectively in said first and second output conditions when said first and second output signal conditions are present at the output terminal means of said comparator means and for operating said buck-boost circuit to produce said zero output condition when said third output signal condition is present at the output terminal means of said comparator means.

4. The converter circuit of claim 1 wherein said comparator means is a bridge-type circuit having first and second signal input terminals and a common point, means for coupling said at least part of said overall combined output between said first input terminal and said common terminal so that the magnitude of the input signal thereat is comparable to said reference signal, and a series circuit of impedance means connected between said first and second input terminals and having first and second tap-off points therealong which are symmetrically related with respect to an intermediate impedance point therebetween which is at zero potential with respect to said common point when the amplitude of the component of said combined output at said first input terminal is equal in value but opposite in polarity to the reference signal at said second input terminal, and means for coupling said reference signal between said second input terminal and said common terminal in an opposite phase to the connection of said overall combined output to said first input terminal so that a loop circuit is formed including said impedance means and said various terminals, and wherein the reference signal and the portion of said overall combined output in the loop circuit produces voltages of opposite polarity at said tap-off points when they are equal in value and voltages of the same polarity where they are of different values, the polarity of which is dependent on whether the reference signal is greater or less than the portion of the overall combined output fed to the loop circuit.

5. The converter circuit of claim 4 wherein said control means comprise logic circuit units responsive to said various voltages at said tap-off points for operating said buck-boost circuit into the proper one of said output conditions to approach a more ideal sinusoidal waveform.

6. The converter circuit of claim 4 wherein the value of the buck-boost circuit added to the outputs of said inverter circuits are of a value to produce an overall combined output which alternates on opposite sides of the ideal desired output and at a relatively high frequency to produce a ripple waveform.

7. The converter circuit of claim 6 wherein said converter circuit further includes means for separating the ripple component of said resultant output signal and feeding the same between said intermediate impedance point of said converter circuit and said common point whereby to increase the ripple frequency rate and to decrease the deviation of said ripple from the ideal desired output.

8. The converter circuit of claim 1 wherein there is provided means responsive to the average value of said overall combined output of the converter circuit for varying the peak amplitude of said reference signal in a direction to stabilize the average value of the converter circuit output.

9. The converter circuit of claim 5 wherein said logic circuit comprises a pair of operational amplifiers each having a negative and a positive input terminal and an output terminal at which a 1 binary signal appears when the positive input terminal is positive with respect to the negative input terminal thereof and a 0 binary signal appears when the positive input terminal is negative with respect to the associated negative input terminal thereof, means respectively coupling the positive input terminal of one of said operational amplifiers and the negative input terminal of the other operational amplifier to said common point, means coupling one of said tap-off points to the positive input terminal of the operational amplifier whose negative input terminal is connected to said common point and coupling the other tap-off point to the negative input terminal of the operational amplifier whose positive input terminal is connected to said common point, a pair of "AND" gates each with a pair of input terminals one of which is coupled to the output terminal of a different one of said operational amplifiers, an exclusive "OR" gate having a pair of inputs respectively coupled to said output terminals of said operational amplifiers, an inverter having an output where the binary signal is the inverse to that fed to its input, the output of said exclusive "OR" gate being connected to the other input terminals of said "AND" gates and to the input of said inverter whereby a 1 binary signal appears at the output of said "AND" gates and said inverter circuit when the signal conditions call for boost, buck and bypass operations respectively, and said buck-boost circuit includes 1 binary signal responsive means for carrying out the required boost, buck and bypass operations.

10. The converter circuit of claim 1 wherein the outputs of said buck-boost circuit during the first and second output conditions thereof are a small fraction of the peak value of the output of said inverter circuit means, whereby the buck-boost circuit provides a small fraction of the power generated by the converter circuit.

11. The converter circuit of claim 1 wherein the voltage produced by the buck-boost circuit is less than 20 percent of the peak value of the output of the inverter means.

12. The converter circuit of claim 1 wherein said DC voltage source means are unregulated.

13. The converter circuit of claim 1 wherein said inverter circuit means produces a stepped sinusoidal-like waveform which alternates above and below the ideal sinusoidal waveform, whereby said buck-boost circuit fills in the gaps between the steps produced by said inverter circuit means.

14. The converter circuit of claim 1 wherein the combined outputs of said inverter circuit means and any filter means associated therewith produce an ideal sinusoidal waveform under normal circuit operating conditions, so that said buck-boost circuit normally operates in said third output condition, said buck-boost circuit becoming operative primarily only under transient or varying load conditions which effect variations in the output of the inverter circuit means.

15. The converter circuit of claim 1 wherein the output of said reference signal source and the portion of said combined output compared thereto are only a small fraction of said combined output of said inverter circuit means, so that the comparator and control means operate at relatively low voltage levels.

16. The converter circuit of claim 9 wherein said buck-boost circuit includes Schmitt trigger circuits coupled respectively to the outputs of said "AND" and exclusive "OR" gates for continuing the signal generated by said gates for a given finite period independently of the time duration of the outputs of said gates.

17. A converter circuit for providing a regulated sinusoidal-like output voltage under varying load current conditions from DC, said converter circuit comprising, in combination:

DC voltage source means capable of delivering a given level of electric power, a source of a reference signal having the desired sinusoidal-like waveform, stepped sinusoidal waveform generating means for providing a stepped waveform output which approaches said desired sinusoidal-like waveform, a buck-boost circuit having a first output condition where the output thereof is a first finite signal of one polarity which is a small fraction of the maximum amplitude of said output, a second output condition where the output thereof is a second finite signal of the same amplitude but opposite polarity to said first finite signal, and a third output condition where the output thereof is zero, means for adding the output of said buck-boost circuit to the output of said stepped sinusoidal waveform generating means to produce an overall combined output, comparator means for comparing said reference signal and at least a part of said overall combined output of said stepped sinusoidal waveform generating means and buck-boost circuit having an amplitude comparable to said reference signal, and control means responsive to said comparator means for operating said buck-boost circuit into one of said output conditions for a desired period which brings said overall resultant output toward the instantaneous level of the desired sinusoidal-like output.