Synchronization control system for firmware access of high data rate transfer bus

• US 4,161,778 A
• Filed: 07/19/1977
• Issued: 07/17/1979
• Est. Priority Date: 07/19/1977
• Status: Expired due to Term

• Current Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Original Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Inventors: Kelley, John H., Rathbun, Donald J., Getson, Edward F. Jr., McLaughlin, Albert T.
• Primary Examiner(s): Springborn, Harvey E.
• Application Number:
  US05/816,985
• Time in Patent Office: 728 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/117
• CPC Class Codes: G06F 13/36 for access to common bus or bus system

Abstract

In a data processing system wherein a plurality of functional units are interconnected by way of a common communication bus in an environment of high data transfer rates, a logic control system is provided for interjecting firmware control during a data transfer between a disk device and main memory to accommodate unsolicited bus requests without incurring data errors or compromising the data transfer rate. Data transferred between the disk device and a disk controller interfacing directly with the common bus is routed through a FIFO (first-in-first-out) buffer under hardware control. The buffer signals the absence of data in its input register and the presence of data in its output register. The signals are logically combined and ANDed with a firmware controlled logic gate to indicate the occurrence of data transfer states. During such transfer states, data is transferred under hardware control between the FIFO buffer and main memory. When the input register of the FIFO buffer is filled during a data transfer from main memory to the disk device, or when the FIFO buffer is empty during a transfer of data from the disk device to main memory, hardware controlled data transfers are not required. In that event the firmware control system is permitted to access the common bus to service unsolicited bus requests.

Claims

1. A data transfer control system for signalling the occurrence of a time period during which an asynchronous common communication bus may be accessed by a firmware control system during a data transfer between a main memory and a mass storage device without compromising the data transfer rate or incurring data errors, said bus electrically linking said main memory, said firmware control system, and a mass storage control unit in electrical communication with a disk adapter controlling the operation of said mass storage device, which includes:

(a) memory means in electrical communication with said disk adapter and said control unit for transferring data asynchronously therebetween and indicating both the presence of input data and the occurrence of a filled condition in said memory means;

(b) logic gate means responsive to the indications from said memory means and control signals from said control unit for providing data strobes to synchronize the flow of data between said memory means and said control unit; and

(c) logic timing means in electrical communication with said control unit and said logic gate means for issuing a control signal to said firmware control system indicating the occurrence of said time period.

2. The combination set forth in claim 1, wherein said memory means is a first-in-first-out buffer having an input register which signals the absence of data and an output register which signals the presence of data.

3. The combination set forth in claim 2, wherein said logic gate means includes:

(a) a first AND gate in electrical communication with said input register and said control unit;

(b) a second AND gate in electrical communication with said output register and said control unit;

(c) an OR gate having inputs connected to the outputs of said first AND gate and said second AND gate;

(d) an even plurality of serially connected inverters connected to the output of said OR gate;

(e) a third AND gate having a first input connected to the output of said plurality of inverters;

(f) a fourth AND gate receiving range and data transfer control signals from said control unit and having an output connected to a second input of said third AND gate; and

(g) a fifth AND gate having a first input connected to the output of said third AND gate and a second input responsive to said logic timing means to provide said data strobes.

4. The combination set forth in claim 3 wherein said logic timing means includes:

(a) a sixth AND gate in electrical communication with said control unit and said disk adapter;

(b) a monostable multivibrator in electrical communication with said control unit;

(c) a NOR gate having one input connected to the output of said OR gate and a second input connected to the output of said fifth AND gate; and

(d) a flip-flop in electrical communication with said NOR gate, and responsive to said multivibrator, said sixth AND gate and said firmware control system, and having one output connected to said second input of said fifth AND gate and a second output in electrical communication with said firmware control system for signalling the occurrence of a time period during which said bus may be accessed.

5. A logic control system operating under the control of both hardware and firmware control means in a data processing system having an asynchronous communication bus electrically linking a main memory, and a disk controller which in turn is in electrical communication with a disk adapter controlling the operation of a mass storage disk system, which includes:

(a) first-in-first-out buffer means in electrical communication with said disk adapter and said disk controller for transferring data asynchronously between said disk system and said main memory;

(b) first logic means responsive to signals from said disk controller and said buffer means for requesting a data transfer between said buffer means and said disk controller; and

(c) second logic means in electrical communication with said firmware control means, said disk controller and said first logic means for signalling the existance of a data transfer time period during which said firmware control means can service bus requests on said common bus without incurring data errors or interfering with the data transfer rate between said disk system and said main memory.