Thin film programmable read-only memory having transposable input and output lines

• US 4,162,538 A
• Filed: 07/27/1977
• Issued: 07/24/1979
• Est. Priority Date: 07/27/1977
• Status: Expired due to Term

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Thornburg, David D.
• Primary Examiner(s): Konick, Bernard
• Assistant Examiner(s): McElheny, Jr., Donald
• Application Number:
  US05/819,310
• Time in Patent Office: 727 Days
• Field of Search: 340/173 SP, 365/96, 365/105, 365/94, 365/103, 365/163, 365/175
• US Class Current: 365/96
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A thin film programmable read-only memory is provided which comprises an X-Y matrix of conductors, the cross points of which are connected together by a switch element comprising a current-controlled negative differential resistance (CNDR) device in series with a semiconductor fuse. At low bias levels corresponding to read signals, the element behaves as a non-linear resistance. At large bias levels corresponding to write signals, the element will be driven to its negative differential resistance characteristic, the switching element becoming a permanent open circuit when the fuse blows. The symmetrical switching characteristics of the CNDR device allows the function of the X conductors (input or address lines) and Y conductors (output or word lines) to be transposed in that the address information can be applied to the Y lines, the output appearing at the X lines.

In an alternate embodiment, a threshold switching (TS) device is utilized in place of the CNDR device.

The current characteristics of the CNDR and TS devices are such that the fuse is blown rapidly and cleanly when the devices are appropriately biased.

Claims

1. A Read only memory comprising:

a matrix of first and second sets of conductors the cross-points of which are connected by non-crystalline semiconductor switches in series with a fuse, each of said switching devices having a symmetrical voltage-current (V-I) characteristic regardless of polarity state and comprises in either polarity state a non-linear high resistance state region and a negative differential low resistance state region, selected ones of said fuses being opened by driving their corresponding switches into said negative differential low resistance state region to provide a rapid rise of current through said fuse whereby a plurality of data words are stored in said memory, and

means for applying a signal of a predetermined magnitude to the input terminal of a preselected conductor of either said first or second set of conductors whereby a signal corresponding to a predetermined data word is provided at the output terminals of the other set of conductors.

2. The read only memory as set forth in claim 1 wherein the V-I characteristic of said switching devices includes a negative differential resistance region between said non-linear high resistance state region and said low resistance state region.

3. The read only memory as defined in claim 1 wherein the low resistance state region of said V-I characteristic is an abrupt transition from said non-linear high resistance state region.

4. The read only memory as defined in claim 1 wherein said first set of conductors comprises n conductors corresponding to n-address lines, each address line has an input terminal associated therewith, and wherein said second set of conductors comprises m conductors corresponding to words of m-bit length, each m conductor having an output terminal associated therewith.

5. The read only memory of claim 4 wherein said signal of a predetermined magnitude is applied to one of said n-address lines, said data word appearing at said output terminals as a m-bit length word.

6. The read only memory of claim 4 wherein said signal of a predetermined magnitude is applied to one of said output terminals, said data word appearing at said input terminals as a n-bit length word.

7. The read only memory as defined in claim 1 wherein said semiconductor switches and fuses are fabricated utilizing thin-film techniques.

8. A programmable read only memory comprising:

a matrix of first and second sets of conductors the cross-points of which are connected by non-crystalline semiconductor switches in series with a fuse, each of said switching devices having a symmetrical voltage-current characteristic regardless of polarity and comprises in either polarity state, a non-linear high resistance state region and a negative differential low resistance state region, said first set of conductors having a plurality of input terminals associated therewith and said second set of conductors having a plurality of output terminals associated therewith, and

means for applying a signal of sufficient magnitude to a selected input terminal whereby a current is caused to flow to selected output terminals causing the fuse associated with the selected input terminal and output terminals to be placed in an open state, said negative differential low resistance state region of said switches being such that a rapid rise in current flows through the fuse causing the fuse to be permanently open, representing a data word stored in said memory.

9. The programmable read-only memory of claim 8 further including means for reading said stored data word by applying a signal of a predetermined magnitude to said selected input terminal whereby said data word appears at said output terminals.

10. The programmable read-only memory of claim 9 wherein a plurality of data words are stored in said memory.

11. A memory matrix comprising an insulating base, a matrix of first and second groups of conductors deposited as a film on one side of said base and arranged so that each conductor of one group crosses over the conductors of the second group forming a plurality of cross points, a switching element at each cross point and comprising a current controlled negative resistance device in series with a fuse, said current controlled negative resistance device having a non-linear high resistance state below a threshold voltage level and a negative differential low resistance state when the applied voltage reaches or exceeds said threshold voltage, said series connected fuse being cleanly placed in an open circuit state by a sudden current rise produced when said current controlled resistance device is driven above said threshold level into said negative different low resistance state causing a rapid rise in fusing temperature which is proprotional to the square of said current rise.

12. The memory matrix of claim 11 wherein said current controlled resistance device includes a transition through a negative differential resistance region between said non-linear high resistance state and said low resistance state upon being driven above said threshold level.

13. The memory matrix of claim 11 wherein said current controlled resistance device region includes an abrupt transition from said non-linear high resistance state upon being driven about said threshold level.

14. The matrix of claim 11 wherein said first group of conductors has a plurality of input terminals associated therewith and said group of conductors has a plurality of output terminals associated therewith, programming means connected to the input and output terminals of said matrix and including addressing means for applying a signal of threshold voltage level to selected of said input terminals and a resistance load factor in selected of said output terminals whereby the fuses of selected cross point switching elements are changed to an open circuit state.