Synchronous phase detected keyboard

• US 4,163,222 A
• Filed: 09/29/1977
• Issued: 07/31/1979
• Est. Priority Date: 02/27/1976
• Status: Expired due to Term

• Current Assignee: Amkey Incorporated
• Original Assignee: Amkey Incorporated
• Inventors: Gove, Donald C.
• Primary Examiner(s): Caldwell, Sr., John W.
• Assistant Examiner(s): Groody, James J.
• Application Number:
  US05/837,653
• Time in Patent Office: 670 Days
• Field of Search: 340/365 C, 340/365 S, 340/365 L, 340/365 R, 197/98, 179/90 K, 323/93, 200/5 A, 200/DIG. 1, 84/DIG. 7, 361/276, 400/479.1
• US Class Current: 341/26
• CPC Class Codes: H03K 17/98 having a plurality of control members, e.g. keyboard
• CPC Class Codes: H03M 11/20 Dynamic coding, i.e. by key scanning H03M11/26 takes precedence

Abstract

For capacitance coupled keyboard data entry means, a key switch, synchronous circuitry and phase detector in combination to yield a unique encoder output signal for a keyboard matrix. Capacitance coupling is effected prior to full key switch travel, that is, coupling actuation prior to full key downtravel and deactuation subsequent to manual key switch release, said key switch having a floating electrical coupling plate inhibited from dropping to a printed circuit board by a fixably positioned magnet. Coupling actuation providing mechanical hysterisis is effected upon key depression by a spring forcing said plate from the magnet and deactuation is effected by the magnet retracting said plate. An analog multiplexer, in synchronization with an encoder are driven by clock counter means to scan the keyboard matrix. The counter further provides distinct high frequency pulse bursts to an actuated coupled connection. High frequency analog multiplexed key switch signals are amplified and transferred upon a single line string having a phase detector in synchronization with the system. The phase detector compares an actuated key reference signal phase to the phase of an actuated key multiplexed signal filtering the latter, the reference phase being derived from said high frequency pulse bursts fed an actuated coupled key switch connection.

Claims

1. In an electronic data processing entry-system, a synchronous phase detected keyboard, comprising in combination:

a printed circuit board whose conductors form a matrix of row coordinates and column coordinates, said row and column coordinates not physically intersecting because of discontinuities in said conductors at each possible intersection point of the matrix;

a plurality of key switch assemblies similarly arranged in a row and column matrix configuration and able to communicate with said printed circuit board, each of said key switch assemblies having an electrically-free floating key switch coupling plate to effect capacitive coupling between a row coordinate and a column coordinate of said printed circuit board at a corresponding possible intersection point of the matrix when said key switch assembly is actuated;

a gating means associated with said row coordinates;

an encoder which sequentially transmits an input signal to said gating means associated with said row coordinates;

a clock means to provide a burst of high frequency pulses which is transmitted to said gating means associated with said row conductors;

said gating means to be turned on by said encoder signal allowing said high frequency pulses to be coupled sequentially into each of the row coordinates;

a reference line which also carries the burst of high frequency pulses generated by said clock means in an alternate path which bypasses the keyboard matrix;

a multiplexer which sequentially addresses each column coordinate of the matrix and receives said burst of high frequency pulses which has been coupled between a particular row coordinate and the column coordinate then being addressed, due to actuation of the appropriate key switch assembly, said multiplexer then transferring the received burst through a single output channel;

a dividing counter means, driven by said clock means, which simultaneously drives said encoder and said multiplexer;

a single string data transference line which receives and carries the output signal from said multiplexer;

a current amplification means upon said single string data transference line to amplify the multiplexer output signal, a phase detection means upon said single string transference line having comparator terminals to receive from said reference line the high frequency pulses and to mix it with the amplified multiplexer output signal to distinguish false signals and generate a characteristic output voltage pulse at an amplitude proportional to the in-phase portion of the multiplexer output signal;

a thresholding amplifier which transmits and amplifies the characteristic voltage pulse generated by said phase detection means only if it exceeds a predetermined threshold, and a read only memory, integrated with said encoder which is driven by the dividing counter means and synchronized so as to be scanning in the same sequence and at the same rate as the multiplexer, and said memory receives and recognizes the amplified characteristic output voltage pulse from said phase detection means via the thresholding amplifier and generates a unique digital code which identifies to the data processing system the particular key switch assembly which has been actuated.

2. The synchronous phase detected keyboard of claim 1 wherein the printed circuit board is an unshielded board having two sets of coordinate plates;

one set of plates receiving input signals from the encoder and being the row coordinates and the other set of plates being addressed by the multiplexer and being the column coordinates, said plates being covered by a thin dielectric layer.

3. The synchronous phase detected keyboard of claim 1 further including a capacitor inserted into the single string data transference line between the threshold amplifier and the read-only-memory to smooth the amplified output voltage pulse generated by said phase detection means.

4. The synchronous phase detected keyboard of claim 1 wherein said gating means includes a plurality of AND gates, each corresponding to a particular row coordinate of the keyboard matrix, each said AND gate being inputted by both the encoder and the clock means, so that transmission through a particular row coordinate is possible only when the clock means pulse burst coincides with the encoder signal at the corresponding AND gate.

5. The synchronous phase detected keyboard of claim 1 wherein said keyswitch assembly further includes:

an insulated integrated shaft and cap movable within an insulated key switch housing;

an integrated key shaft platform base forming the lower extent of said shaft, the edges of said base slidably communicating with said housing;

a magnet fixably displaced horizontally above said printed circuit board;

support means to secure said magnet within said housing;

an electrically free-floating coupling plate capable of providing a capacitive coupling with said printed circuit board, said coupling plate being restrained by said magnet;

said magnet having strength to retract said coupling plate from said circuit board;

said platform base having legs downwardly protruding from its corners, said legs being capable of extending past and below said magnet and support means to contact said coupling plate, both the platform base and the legs slidably communicating with said keyswitch housing to prevent lateral movement.