Address management system

• US 4,163,280 A
• Filed: 06/17/1977
• Issued: 07/31/1979
• Est. Priority Date: 06/30/1976
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Electric Co., Ltd.
• Original Assignee: Tokyo Shibaura Electric Co., Ltd.
• Inventors: Mori, Ryuichi, Ichikawa, Tadao, Shiraogawa, Yukio
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Sachs, Michael C.
• Application Number:
  US05/807,500
• Time in Patent Office: 774 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/207
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

An address management system includes a central processing unit (CPU) and an address management unit arranged between a direct memory device (DMA) and a main memory unit to control memory access from the CPU and DMA. Segment registers for address expansion are provided in the CPU and DMA, respectively. The address management unit includes a conversion table for converting logical address data and segment data and segment data from the CPU and DMA into a corresponding physical address data, and the conversion table includes a bit position for detecting an address error and a control bit for selecting a memory access to a local memory or a shared memory.

Claims

1. In a data processing system comprising a main memory unit including a local and shared memory, a central processing unit for executing a program including a first register having first logical addresses and segment registers comprising segment block data for address expansion, and direct memory access devices adapted to gain direct access to the main memory unit each including a second register having second logical addresses and a segment register comprising segment block data for address expansion,

an address management unit for controlling access to either the local or shared memory by the central processing unit or direct memory access devices comprising a conversion table for converting logical addresses selectively received from the segment registers and first and second registers of the central processing unit and direct memory access devices into physical addresses for accessing the main memory unit.

2. A data processing system according to claim 1, in which said address management unit includes a conversion table of predetermined bit configuration adapted to convert logical address data sent thereto from the central processing unit and direct memory access device to physical address data for designating the local and shared memories.

3. A data processing system according to claim 2, in which said conversion table includes a predetermined bit for designating an access to the local memory or the shared memory.

4. A data processing system according to claim 2, in which said conversion table includes a predetermined bit for designating an access to the local memory.

5. A data processing system according to claim 2, in which said conversion table includes a predetermined bit for designating the shared memory.

6. A data processing system according to claim 2, in which said conversion table includes a first predetermined bit for designating an access to the local memory or the shared memory, and a second predetermined bit for detecting an address error delivered from the conversion table.

7. A data processing system according to claim 2, in which said conversion table includes a first predetermined bit for designating an access to the local memory and a second predetermined bit for detecting an address error delivered from the conversion table.

8. An address management system according to claim 2, in which said conversion table includes a first predetermined bit for designating an access to the shared memory and a second predetermined bit for detecting an address error delivered from the conversion table.

9. An address management system according to claim 2, in which said conversion table includes a first predetermined bit for designating an access to the local memory, a second predetermined bit for designating an access to the shared memory and a third predetermined bit for detecting an address error delivered from the conversion table.

10. An address management system according to claim 1, in which said central processing unit includes at least two segment registers so as to effect an address expansion.

11. An address management system according to claim 10, in which one of the two segment registers is used for instruction fetch and the other is used in a predetermined timing for operand fetch.

12. An address management system according to claim 10, in which at least one of the two segment registers is used for instruction fetch.

13. An address management system according to claim 10, in which at least one of the two segment registers is used for operand fetch.

14. A data processing system according to claim 1, in which said address management unit includes interruption means adapted to, when an address error is detected at a first predetermined bit position of a conversion table for converting the logical address data to physical address data, send an interruption signal to the central processing unit when a first predetermined bit data appears at the first bit position of the conversion table, and memory selection means for selecting either one of the local memory and shared memory when a second predetermined bit data is delivered at the second bit position of the conversion table.

15. A data processing system according to claim 14, in which said interruption includes an inverter for inverting the first predetermined bit data, and a NAND gate for NANDing an output of the inverter and a timing signal from the central processing unit.

16. A data processing system according to claim 14, in which said memory selection means includes an inverter for inverting the second predetermined bit data, a first NAND gate for designating an access to the local memory by NANDing the output of the inverter and a control signal from the central processing unit, and a second NAND gate for designating an access to the shared memory by NANDing the second predetermined bit data and a control signal from the central processing unit.

17. A data processing system according to claim 14, in which said memory selection means includes a first NAND gate for designating an access to the local memory by NANDing a first predetermined bit data from the conversion table and a control signal from the central processing unit, and a second NAND gate for designating an access to the shared memory by NANDing a second predetermined bit data from the conversion table and the control signal from the central processing unit.

18. A data processing system for use in a computer memory, comprising a central processing unit including a first segment register used for instruction fetch and adapted to store a first segment data, a second segment register used for operand fetch and adapted to store a second segment data and a first memory address register for storing a first logical block data and a first displacement data;

a direct memory access device including a third segment register for storing a third segment data and a second memory address register for storing a second logical block data and a second displacement data; and

an address management system comprising an address management unit including a first change-over circuit for selecting any one of the first, second and third segment data, a second change-over circuit for selecting any one of the first and second logical block data, a conversion table for converting a segment data from the first change-over circuit and a logical block data from the second change-over circuit to a corresponding physical block data, and a third address register for storing a physical block data from the conversion table and any one of the first and second displacement data so as to represent an actual physical memory address.

19. A data processing system for use in a computer memory, comprising a main memory unit including a local memory and a shared memory;

a central processing unit for effecting a data transfer to and from the main memory unit so as to execute a program;

direct memory access devices adapted to gain direct access to the main memory unit;

a conversion table of word bit configuration adapted to convert logical address data designated from the central processing unit and direct memory access device into a corresponding physical address data and including a first predetermined bit for detecting an address error and a second predetermined bit for gaining access to the main memory unit;

means adapted to, when an address error is detected, send an interruption signal to the central processing unit and including an inverter for inverting the first predetermined bit data and a NAND gate for NANDing the output of the inverter and a timing signal from the central processing unit; and

means adapted to select an access to the local memory or the shared memory and including an inverter for inverting the second predetermined bit data, a first NAND gate for NANDing the output of the inverter and a control signal from the central processing unit and a second NAND gate for NANDing the second predetermined bit data and the control signal for the central processing unit.

20. A data processing system for use in a computer memory, comprising memory means including first and second memory units;

a central processing unit for effecting a data transfer to and from the memory so as to execute a program;

a conversion table of word bit configuration adapted to convert logical address data designated from the central processing unit and direct memory access device into a corresponding physical address and including a first predetermined bit for detecting an address error, a second predetermined bit for gaining access to the first memory unit and a third predetermined bit for having access to the memory unit;

means adapted to send an interruption signal to the central processing unit and including an inverter for inverting the first predetermined bit data and a NAND gate for NANDing the output of the inverter and a timing signal from the central processing unit; and

means adapted to select an access to the first memory unit or the second memory unit and including a first NAND gate for NANDing a third predetermined bit data and a control signal from the central processing unit which is generated when the second memory unit is down and a second NAND gate for NANDing a second predetermined bit data and a control signal from the central processing unit which is generated when the first memory unit is down.