Control circuit for load-leveling shock absorbers

• US 4,164,664 A
• Filed: 12/13/1977
• Issued: 08/14/1979
• Est. Priority Date: 12/13/1977
• Status: Expired due to Term

• Current Assignee: Stanley J. Kasiewicz
• Original Assignee: Stanley J. Kasiewicz
• Inventors: Kasiewicz, Stanley J.
• Primary Examiner(s): Hix, L. T.
• Assistant Examiner(s): Schreyer, S. D.
• Application Number:
  US05/860,276
• Time in Patent Office: 609 Days
• Field of Search: 307/118, 307/10 R, 307/246, 280/707, 280/6 H, 280/6.1, 280/6 R, 280/DIG. 1, 91/35
• US Class Current: 307/118
• CPC Class Codes: B60G 17/01933 Velocity, e.g. relative velocity-displacement sensors
• CPC Class Codes: B60G 17/0523 Regulating distributors or valves for pneumatic springs
• CPC Class Codes: B60G 2202/314 The spring being a pneumatic spring
• CPC Class Codes: B60G 2204/111 on pneumatic springs
• CPC Class Codes: B60G 2204/112 on dampers, e.g. fluid dampers
• CPC Class Codes: B60G 2400/252 vertical
• CPC Class Codes: B60G 2401/14 Photo or light sensitive means, e.g. Infrared
• CPC Class Codes: B60G 2401/26 Resistance type, e.g. as level indicator
• CPC Class Codes: B60G 2600/02 Retarders, delaying means, dead zones, threshold values, cut-off frequency, timer interruption
• CPC Class Codes: B60G 2600/74 Analog systems
• CPC Class Codes: Y10S 280/01 Load responsive, leveling of vehicle

Abstract

A control circuit for an air-spring shock absorber controls pressurization or depressurization of the air chamber of the shock absorber in response to the output signal condition of a level sensor. The control circuit includes a first signal path that conditions the operation of an air pump for pressurizing the air chamber, and a second signal path that conditions the operation of an exhaust valve for depressurizing the air chamber. A timing circuit delays the enablement of the air pump and exhaust valve until the level sensor output signal condition associated with the actuation of the pump or valve has existed for a minimum predetermined time period. The timing circuit includes an R-C time delay circuit with an instant reset to avoid cumulative signal build-up. The control circuit is comprised of a set of digital logic gates which are preferably implemented by standard integrated circuit chips.

Claims

1. A control circuit for use in the pressure regulation of a pressurized load-leveling device, the load-leveling device being equipped with detector means having first and second output signals for providing a first signal condition to represent underpressurization, a second signal condition to represent overpressurization, and a third signal condition to represent proper pressurization, the control circuit comprising:

a first control channel including first logic gate means having first and second input terminals which are adapted to receive the first and second output signals of the detector means without difference as to order, and which is responsive to the first signal condition to provide a first output signal for conditioning the operation of pressurizing means to increase the pressure in the load-leveling device;

a second control channel including second logic gate means having first and second input terminals which are adapted to receive the first and second output signals of the detector means without difference as to order, and which is responsive to the second signal condition to provide a second output signal for conditioning the operation of depressurizing means to decrease the pressure in the load-leveling device; and

timing circuit means, intercoupled with said first and second control channels and responsive to the occurrence of a first or second output conditioning signal from the first or second logic gate means when said first and second output conditioning signal is continuous for a minimum predetermined time duration, for providing an enabling signal to the first and second control channels, which, in conjunction with the first or second output signal, enables the operation of the pressurizing or depressurizing means, respectively.

2. The control circuit as defined in claim 1 wherein the timing circuit means comprises,

third logic gate means, responsive to the occurrence of an output conditioning signal, for changing the signal level of its output in response thereto, and

R-c timing network means, responsive to a change in the signal level of the output of the third gate means for developing a related signal level output through a predetermined time delay to provide an enabling signal to the control channel associated with the conditioning signal.

3. The control circuit as defined in claim 2 wherein the R-C timing network means comprises the serial connection of a resistance and capacitance, and further including reset means comprising a diode connected parallel with the resistance.

4. The control circuit as defined in claim 1 wherein the control circuit implementation includes a quad-NOR integrated circuit chip and a quad-NAND integrated circuit chip.