Digital control system with Boolean processor

• US 4,165,534 A
• Filed: 06/01/1978
• Issued: 08/21/1979
• Est. Priority Date: 04/25/1977
• Status: Expired due to Term

• Current Assignee: Allen-Bradley Company (Rockwell Automation, Inc.)
• Original Assignee: Allen-Bradley Company (Rockwell Automation, Inc.)
• Inventors: Dummermuth, Ernst, Grudowski, Raymond A., Grants, Valdis, Schmidt, Otomar
• Primary Examiner(s): Chapnick, Melvin B.
• Application Number:
  US05/911,520
• Time in Patent Office: 446 Days
• Field of Search: 364/900 MS File, 364/ 200 MS File, 364/104, 364/107
• US Class Current: 700/3
• CPC Class Codes: G05B 19/052 Linking several PLC's
• CPC Class Codes: G05B 2219/1103 Special, intelligent I-O processor, also plc can only access via processor
• CPC Class Codes: G05B 2219/1159 Image table, memory
• CPC Class Codes: G05B 2219/1204 Multiprocessing, several plc's, distributed logic control
• CPC Class Codes: G05B 2219/13128 Relay ladder diagram, RLL RLD KOP
• CPC Class Codes: G05B 2219/15048 Microprocessor
• CPC Class Codes: G05B 2219/15127 Bit and word, byte oriented instructions, boolean and arithmetic operations

Abstract

An eight-bit microprocessor sequentially reads controller type instructions from a memory and applies the operation codes of selected ones of the instructions to a hardwired Boolean processor. The microprocessor also couples status words between an I/O image table stored in the memory and the I/O interface racks which connect the programmable controller to the machine being controlled. In general, those controller type instructions which are word oriented are executed by the microprocessor and those which are single-bit oriented are executed by the Boolean processor. The Boolean processor is operable in combination with the microprocessor to examine selected status bits in the I/O image table and to set selected status bits therein to a logic state which is determined in part by the state of the examined status bits.

Claims

1. A programmable controller comprising:

a memory which stores on selected memory lines an I/O image table comprised of a plurality of multi-bit status words, a plurality of controller instructions which comprise a control program, and a set of machine instructions;

an address bus connected to said memory to select a memory line therein;

a data bus connected to said memory to couple data to and from said memory;

an I/O interface rack coupled to said address bus and said data bus, said I/O interface rack including input and output circuits for coupling the data bus to sensing devices and operating devices on a machine to be controlled;

a microprocessor responsive to selected machine instructions to sequentially read said controller instructions out of said memory, responsive to other selected machine instructions to read selected status words out of said memory, responsive to other machine instructions to write status words into selected memory lines of said I/O image table, and responsive to other machine instructions to couple status words between said I/O image table and associated input and output circuits in said I/O interface rack; and

a Boolean processor coupled to said data bus and including;

a. a logic unit having an input and an output and including a first single-bit storage means having an input coupled to the logic unit input and an output coupled to the logic unit output, said logic unit being operable to store a logic state which corresponds to the logic state of a signal coupled to said logic unit input and being operable to couple said stored logic state to said logic unit output;

b. bit pointer means having inputs connected to leads in said data bus and being operable to couple the logic state signal of a selected one of said data bus leads to the input of said logic unit; and

c. bit selector means having an input connected to said logic unit output and a plurality of outputs connected to leads in said data bus, said bit selector means being operable in response to a machine instruction executed by said microprocessor to couple the logic state at said logic unit output to one of said leads in said data bus; and

in which the logic unit includes a second single-bit storage means having an input coupled to the logic unit input and an output coupled to the input of said first single-bit storage means, first gate means operable when enabled to couple the logic state of said logic input to said first single-bit storage means, second gate means operable when enabled to couple the logic state of said logic unit input to said second single-bit storage means, and third gate means operable when enabled to couple the logic state of said second single-bit storage means output to the input of said first single-bit storage means.

2. The programmable controller as recited in claim 1 in which said Boolean processor includes decoder means connected to receive operation codes within selected ones of the controller instructions read from said memory and is responsive to selective ones of said operation codes to enable said first, second and third gate means in said logic unit.

3. A programmable controller comprising:

a random access memory which stores a plurality of macro-instructions which comprise a control program, each of said macro-instructions including a selected one of a plurality of types of operation codes;

a read-only memory which stores a first set of machine instructions which comprise a macro-instruction decoding routine, and a plurality of sets of machine instructions which comprise macro-instruction execution routines, there being a unique macro-instruction execution routine associated with each type of macro-instruction operation code;

an address bus connected to said random access memory and said read-only memory to select a line therein;

a data bus connected to said random access memory to couple data to and from said random access memory and connected to said read-only memory to couple data from said read-only memory;

an I/O interface rack coupled to said address bus and said data bus, said I/O interface rack including input and output circuits for coupling the data bus to sensing devices and operating devices on a machine to be controlled; and

a microprocessor for executing machine instructions, said microprocessor being connected to said data bus and said address bus and having a program counter which stores the memory address of a machine instruction stored in said read-only memory and a stack pointer register which stores the address of a macro-instruction stored in said random access memory, said microprocessor being responsive to selected machine instructions in said macro-instruction decoding routine to read out of said random access memory the macro-instruction addressed by said stack pointer register and being responsive to further selected machine instructions in said macro-instruction decoding routine and the operation code in the macro-instruction read from said random access memory to load the starting address of the macro-instruction execution routine which is associated with said operation code into said program counter.

4. The programmable controller as recited in claim 3 in which an I/O image table comprised of a plurality of multi-bit status words is stored in said random access memory and in which a macro-instruction execution routine associated with an operation code in one of said macro-instructions includes machine instructions which direct said microprocessor to couple data between said I/O image table and said I/O interface rack.

5. The programmable controller as recited in claim 3 in which a mapping table comprised of a list of the starting addresses of all the macro-instruction execution routines is stored in said read-only memory and said microprocessor loads the starting address of the macro-instruction execution routine which is associated with said operation code into said program counter by reading it from said mapping table and coupling it through said data bus to said program counter.

6. The programmable controller as recited in claim 3 in which a Boolean processor is coupled to said microprocessor, said Boolean processor being responsive to selected ones of said macro-instruction operation codes read from said random access memory to perform corresponding logical operations, and said Boolean processor including means for resetting said microprocessor program counter to the starting address of said macro-instruction decoding routine after said Boolean processor performs its logical operation.

7. A programmable controller comprising:

a memory which stores a plurality of control instructions which comprise a control program, each of said control instructions including an operation code and selected ones of said control instructions including an associated bit pointer;

a microprocessor connected to said memory through an address bus and a multi-lead data bus, said microprocessor being operable to sequentially read said control instructions out of said memory onto said data bus; and

a Boolean processor which comprises;

a. means coupled to said data bus for decoding selected ones of said operation codes,

b. bit selector means having inputs connected to said data bus and being responsive to the bit pointer in selected ones of said control instructions read from said memory to selectively couple the logic state on one of said data bus leads to a bit selector output terminal,

c. main decision storage means having an input terminal coupled to said bit selector output terminal, an enable terminal connected to said decoding means and an output terminal, said main decision storage means being responsive to selected decoded operation codes to store a logic state indicative of the logic state of said bit selector output terminal, and

d. second bit selector means having an input terminal coupled to said main decision storage means output terminal, having a plurality of output terminals coupled to respective leads in said multi-lead data bus, and having an enable terminal coupled to said decoding means, said second bit selector means being responsive to selected decoded operation codes and their associated bit pointer to couple the logic state of said main decision storage means to a selected one of said data bus leads; and

in which said Boolean processor includes gate means having one input coupled to said main decision storage means, a second input coupled to said microprocessor, and an output terminal connected to one lead in said data bus, said microprocessor being operable to enable said gate means to couple the logic state of said main decision storage means to said one data bus lead.

8. The digital control system as recited in claim 7 in which said Boolean processor includes second gate means having one input terminal coupled to a selected one of said data bus leads, a second input coupled to said processor, and an output coupled to said main decision storage means, said processor being operable to enable said second gate means to couple the logic state of said one data bus lead to said main decision storage means.

9. A digital control system comprising:

memory means which stores on selected memory lines a plurality of controller instructions which comprise a control program, a plurality of multi-bit status words which comprise an I/O image table, and a set of machine instructions;

an address bus connected to said memory means to select a memory line therein;

a multi-lead data bus connected to said memory means to couple data to and from said memory means;

an I/O interface rack coupled to said address bus and said data bus, said I/O interface rack including input and output circuits for coupling the digital control system to sensing devices and operating devices on a machine to be controlled;

processor means responsive to selected machine instructions to sequentially read said controller instructions out of said memory means, responsive to other selected machine instructions to read selected status words out of said I/O image table, responsive to other selected machine instructions to write status words into selected memory lines of said I/O image table, and responsive to other machine instructions to couple status words between said I/O image table and said I/O interface rack; and

a Boolean processor coupled to said data bus and said processor means, said Boolean processor being responsive to control signals from said processor means to perform a set of single-bit calculations on selected status bits in said I/O image table which are coupled to it through said multi-lead data bus, and which are to generate a single-bit result on a selected lead in said multi-lead data bus, which result is coupled to said I/O image table.

10. The digital control system as recited in claim 9 in which said Boolean processor includes a set of terminals for receiving a bit pointer code contained in selected ones of said controller instructions and said Boolean processor is responsive to a bit pointer code received at said set of terminals to select one of the leads in said multi-lead data bus.