Status reporting

• US 4,167,041 A
• Filed: 04/05/1977
• Issued: 09/04/1979
• Est. Priority Date: 04/05/1977
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Rehage, Ted A., Curlander, Paul J.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Chan, Eddie
• Application Number:
  US05/784,751
• Time in Patent Office: 882 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 714/48
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/327 Alarm or error message display

Abstract

In a plural unit system, particularly of the data processing type, controlled units such as tape drives, constitute status reporting units (SRUs) which report status including error conditions to one or more status analyzing units such as computers (CPUs), programmable controllers, and the like. Each of the SRUs has a register, such as a shift register, associated therewith for receiving error status indications. The signal state of the shift register when all zeros indicates error-free status, any nonzero state signifies an error. An OR circuit receives signals from all of the bit positions of each of the respective shift registers and combines same into an SRU group error indicating signal. A second register, also a shift register, associated with the respective SRUs receives the output of the OR circuit in one of its bit positions, the bit position indicating the address of the reporting SRU. The output of the two shift registers associated with each of the SRUs are serialized onto one wire and supplied to an intermediate shift register. Combined signal status in the intermediate shift register are then supplied to one or more status analyzing units in a two byte format, i.e., one byte for the address and a second byte for the error status. An appropriate status analyzing unit then determines the error condition of the SRU. If more than one SRU is in error, then the address byte will have more than one binary one indicating state requiring further analysis by the respective status analyzing units.

Claims

1. A status reporting apparatus comprising,

an addressable unit,

a first register having a plurality of stages for receiving status signals to be reported from said addressable unit,

a second register having a plurality of stages,

a first OR circuit receiving status signals from said first register and supplying a status group signal to one stage of said second register having a position within said second register indicating address of said addressable unit.

2. The apparatus set forth in claim 1 further including a plurality of said addressable units and a corresponding plurality of said first and second registers respectively for receiving status signals from said addressable units, and a plurality of said first OR circuits interconnected such that each of said second registers receives said status group signal in a unique stage position, and

a circuit connected to output portions of all said first OR circuits for receiving said status group signal for supplying an alert signal.

3. The apparatus set forth in claim 2 including a control circuit for generating a degating signal to said addressable units for inhibiting the supplying of said status signals and including means for supplying shift signals to said first and second registers for transferring signal contents thereof, and

a common line for receiving transferred signal contents.

4. The apparatus set forth in claim 3 further including an attachment unit and a controlling unit and signal connections therebetween.

a shift register in said attachment unit connected to said single line for receiving said shifted signal contents, and

means transferring said shifted signal contents from said one shift register to one of said controlling unit.

5. The apparatus set forth in claim 4 wherein all of said registers are shift registers each of said shift registers being respectively associated with one of said addressable units having a single output connection to said single line whereby the signal contents of all of said associated shift registers are combined as a single set of signals.

6. The apparatus set forth in claim 5 further including an alert line connected to said controlling unit and to all of said first OR circuits for receiving signals thereover for alerting said controlling unit that error status is to be reported.

7. The apparatus set forth in claim 6 wherein said connection between said attachment unit and said controlling unit includes a set of tag out lines, a set of bus out lines, and a set of bus in lines,

said control circuit being responsive to signals received over said tag out lines to indicate that status signals are to be reported and for activating said degating means for degating said addressable units, and

circuit means connected to said bus out for receiving signals therefrom and for supplying shift signals to said first and second registers for shifting same through said attachment unit to said controlling unit, and the connection of said bus out to said shifting line being controlled by said tag out lines.

8. The apparatus set forth in claim 1 wherein said first and second registers are shift registers interconnected to form a single shift register train and an output connection being connected to one of said shift registers for receiving a serial train of the signal contents of both of said registers whereby a train of signals indicates status and address from said registers.

9. The apparatus set forth in claim 8 further including a plurality of said first OR circuit and a plurality of output terminals respectively connected to said first OR circuit for supplying an alert signal indicating said first register contains status signals to be reported.

10. The apparatus set forth in claim 9 including the plurality of said first and second register connections wherein all of said output terminals are connected to a common line for generating a single alert signal and all of said output connections being connected to a single line whereby signal contents of all of said first and second registers are merged as a single signal set of status.

11. A data processing status reporting system for reporting status to a controlling unit from one of a plurality of status reporting units SRU comprising,

an attachment unit electrically interposed between said controlling unit and each of said SRUs and having a shift register for receiving status signals, and means for transferring said received status signals to said controlling unit from said shift register,

each of said SRUs including at least a first register for containing error status signals indicating error status in the respective SRUs,

Or circuits each connected to predetermined stages of each of said first registers for indicating error status in a respective one of said SRUs, and means connecting said OR circuits to said controlling unit for indicating detected error status in one of said SRUs, and a single line connection between all of said registers and said attachment unit shift register for receiving status signals simultaneously from all of said registers through said single shift register in said attachment unit.

12. A data processing system set forth in claim 11 further including at least one second register having a plurality of stages, said respective OR circuits being connected to respective ones of said stages indicating an address of an SRU supplying status signals to a respective one of said first registers, and means for shifting the signal content of said first and second registers through said single shift register of said attachment unit as a set of status signals which include address signals.

13. A data processing system set forth in claim 12 wherein a second register is associated with each of said SRUs and having a serial shifting connection with the respective ones of said first registers, each of said separate second registers being connected to a respective one of said OR circuits for receiving a signal to one and only one of its stages for indicating an address of the corresponding or associated SRU, and

means for simultaneously shifting signal content of all of said first and second registers to said single shift register in said attachment unit.

14. The data processing system set forth in claim 13 further including tag out lines and bus out lines extending from said controlling unit to said attachment unit, and bus in lines extending from said attachment unit to said controlling unit, a decode circuit in said attachment unit responsive to predetermined tag out signals on said tag out lines for indicating degating of said SRUs connected to said attachment unit, and timing circuit means responsive to said tag decode circuit to pass signals from said bus out line to shift the signal contents of all of said shift registers and said one shift register synchronously with signals on said bus out lines, and other circuits connected to said bus in, bus out and tag lines for performing other data processing operations.

15. A status reporting system for a plural unit system, including in combination:

a plurality of status reporting units (SRU), each said SRU having a status shift register and an address shift register, circuit means responsive to said status register having a predetermined signal content to set said address register to a predetermined address indicating said SRU,

a status accumulating shift register (SASR) for receiving status signals and having a common input,

a status connection shift register (CSR),

an alert line connected to said SRU status shift registers for receiving a predetermined logic sum of signal contents therefrom for indicating that status is to be reported,

shift means connecting said SRU status shift register to said common input, said SASR to said CSR, whereby signal contents of all said shift registers are shiftable through said CSR, and

utilization means connected to said CSR for receiving signals therefrom.

16. The system set forth in claim 15 further including a plurality of said CSRs all connected to said SASR for receiving signals from said SASR and a plurality of said utilization means respectively connected to each said CSR.

17. The system set forth in claim 16 further including timing signal lines extending from one of said utilization means to all of said shift registers for timing said shifting of all said shift registers.