Source follower circuit using FETs

• US 4,168,471 A
• Filed: 04/13/1978
• Issued: 09/18/1979
• Est. Priority Date: 04/15/1977
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Sampei, Tohru
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US05/895,986
• Time in Patent Office: 523 Days
• Field of Search: 330/264, 330/269, 330/277, 330/300, 330/295
• US Class Current: 330/264
• CPC Class Codes: H03F 3/3001 with field-effect transistors
• CPC Class Codes: H03F 3/505 with field-effect devices

Abstract

A source follower circuit using at least one FET in which an end of a resistor element is connected to the gate terminal of the FET and the other end of the resistor element is connected to a signal source which generates a comparatively large AC input signal. The resistance of the resistor element is determined to be at such a value as to prevent oscillation of the FET which is likely to occur depending on the length of the wiring between the signal source and gate terminal and the length of wiring between the source terminal and a load.

Claims

1. A source follower circuit using at least two FETs each having a gate terminal, a drain terminal and a source terminal, said source follower circuit comprising a load resistor with one end thereof connected to said each source terminal, a power supply connected for applying a predetermined voltage between the other end of said load resistor and said each drain terminal, a signal source with one end thereof connected to the other end of said load resistor, at least two resistors connected in series between the other end of said signal source and the gate terminal of one of said FETs, and a series connection between a junction point of said at least two resistors and the gate terminal of the other of said FETs.

2. A source follower circuit according to claim 1, in which all of said at least two FETs are power MOSFETs.

3. A source follower circuit according to claim 2, wherein the input resistance of said power MOSFETs is negative, and the values of said at least two resistors are set to compensate for this negative input resistance so that the input resistance of the source follower circuit viewed from the signal source is positive.

4. A source follower circuit comprising:

at least two power MOSFETs including an N-channel and a P-channel MOSFET, each having a gate terminal, a drain terminal and a source terminal;

a load resistor with one end thereof connected to said source terminals;

a first power supply connected for applying a predetermined voltage between the other end of said load resistor and the drain terminal of one of said MOSFETs;

a second power supply connected for applying a predetermined voltage between the other end of said load resistor and the drain terminal of the other of said MOSFETs;

a first resistor component with one end thereof connected to the drain terminal of said one of said MOSFETs;

a resistor with one end thereof connected to the other end of said first resistor component;

a transistor with a collector terminal thereof connected to the other end of said resistor, said transistor having an emitter terminal thereof connected to the drain terminal of said other of said MOSFETs;

a first D.C. connection between a junction point of said first resistor component and said resistor and the gate terminal of said one of said MOSFETs;

a second D.C. connection between a junction point of said resistor and the collector of said transistor and the gate terminal of said other of said MOSFETs; and

a signal source connected to the base terminal and the emitter terminal of said transistor,

wherein the input resistance of the power MOSFETs is negative, and the values of the first resistor component and the resistor are set to compensate for this negative input resistance so that the input resistance of the source follower circuit viewed from the signal source is positive.

5. A source follower circuit according to claim 4, in which said first D.C. connection includes a second resistor.

6. A source follower circuit according to claim 4, in which said second D.C. connection includes a third resistor.

7. A source follower circuit according to claim 6, further comprising:

a first series circuit comprising a fourth resistor and a MOSFET coupled between the junction point of the first D.C. connection and the load resistor; and

a second series circuit comprising a fifth resistor and a MOSFET coupled between the junction of the second D.C. connection and the load resistor.

8. A source follower circuit comprising:

at least two power MOSFETs including an N-channel MOSFET and a P-channel MOSFET, each having a gate terminal, a drain terminal and a source terminal;

a load resistor with one end thereof connected to both of said source terminals;

a first power supply connected for applying a predetermined voltage between the other end of said load resistor and the drain terminal of one of said MOSFETs;

a second power supply connected for applying a predetermined voltage between the other end of said load resistor and the drain terminal of the other of said MOSFETs;

a signal source with one end thereof connected to the other end of said load resistor;

a first resistor with one end thereof connected to the gate terminal of said one of said MOSFETs;

a first bias power supply connected between the other end of said first resistor and the other end of said signal source;

a second resistor with one end thereof connected to the gate terminal of said other of said MOSFETs; and

a second bias power supply connected between the other end of said second resistor and the other end of said signal source,

wherein the input resistance of the power MOSFETs is negative, and the values of the first and second resistors are set to compensate for this negative input resistance so that the input resistance of the source follower circuit viewed from the signal source is positive.

9. A source follower circuit comprising:

at least two power MOSFETs including an N-channel MOSFET and a P-channel MOSFET, each having a gate terminal, a drain terminal and a source terminal;

a load resistor with one end thereof connected to both of said source terminals;

a first power supply connected for applying a predetermined voltage between the other end of said load resistor and the drain terminal of one of said MOSFETs;

a second power supply connected for applying a predetermined voltage between the other end of said load resistor and the drain terminal of the other of said MOSFETs;

a signal source with one end thereof connected to the other end of said load resistor;

a first resistor with one end thereof connected to the gate terminal of said one of said MOSFETs;

a second resistor with one end thereof connected to the gate terminal of said other of said MOSFETs;

a transistor driving network having outputs coupled to the other ends of said first and second resistors; and

a bias network coupled between inputs of the transistor driving network and the signal source,

wherein the input resistance of the power MOSFETs is negative, and the values of the first and second resistors are set to compensate for this negative input resistance so that the input resistance of the source follower circuit viewed from the signal source is positive.