Multiport conference circuit

• US 4,175,215 A
• Filed: 12/05/1977
• Issued: 11/20/1979
• Est. Priority Date: 12/05/1977
• Status: Expired due to Term

• Current Assignee: GTE Automatic Electric Laboratories Incorporated
• Original Assignee: GTE Automatic Electric Laboratories Incorporated
• Inventors: McLaughlin, Donald W., Fetterer, Gerald F.
• Primary Examiner(s): Caldwell, Sr., John W.
• Assistant Examiner(s): Myer, Daniel
• Application Number:
  US05/857,168
• Time in Patent Office: 715 Days
• Field of Search: 340/147 R, 179/18 BC, 179/15 AT, 179/1 CN
• US Class Current: 370/261
• CPC Class Codes: H04M 3/569 using the instant speaker's algorithm speech detection per se G10L25/78

Abstract

An improved conference technique whereby a number of channels in a telephone switching system employing pulse code modulation for transmission purposes are combined so that a number of subscribers may participate in a common telephone conversation. The conference circuit is provided with a continuous threshold to pass the primary signal and to exclude the reflection. It is only used in the selection process, and for conditions which do not provide the threshold being met, the previous speaker is retained.

Claims

1. In a pulse code modulated communication system, a plurality of communication channels arranged on a multiplexed basis, a switching system including a memory access by said communication channels and a conference circuit including, a first register connected to said memory operated to store the coded value of information from each of said channels conducted sequentially through said memory;

a second register connected to said first register and including an output circuit;

a first comparator circuit connected to said first and to said second registers operated to compare the coded value of information stored in said first and said second registers and in response to determination that the value of information stored in said first register is less than the value of information stored in said second register to provide an output signal;

counting means connected to said memory periodically incremented in response to signals from said memory, a fourth register connected to said counting means operated to store the count of said counting means, a fifth register connected to said fourth register, said count stored in said fourth register transferred to said fifth register in response to signals from said switching system, a second comparator circuit connected to said fourth and fifth registers operated in response to a determination that the count stored in said fourth and fifth registers are equal to provide an output signal;

a third comparator circuit connected to said fourth and fifth registers operated in response to determination that the count stored in said fourth and fifth registers are equal to provide an output signal;

a sixth register connected to the output of said second register and having an output to said switching system operated in response to a signal from said switching system for transfer of said coded value of information in said second register to said channels under control of said switching system;

a first threshold comparator, the contents of said first register being connected to said first threshold comparator and the latter providing an output when said first register achieves an established threshold;

a second threshold comparator, the contents of said second register being connected to said second threshold comparator and the latter providing an output when said second register achieves said established threshold; and

gating means connected to said first, second and third comparator circuits and to said first and second threshold comparators selectively operated in response thereto to provide an output signal to update, said update signal being coupled to said first and second registers to operate them to transfer the coded value of information stored in said first register into storage in said second register, said update signal further being coupled to said first counting means to operate the latter to transfer the count in said first counting means into storage in said second counting means.

2. In a pulse code modulated communication system as claimed in claim 1, wherein:

said gating means comprise a plurality of gate circuits including a first gate circuit connected to said second and third comparator circuit and a second gate circuit connected to said first comparator circuit and to said first gate circuit, said first and second gate circuits being selectively operated to cause said update signal to occur when neither said second and third comparator circuits provide an output signal and said first comparator circuit does provide an output signal.

3. In a pulse code modulated communication system as claimed in claim 1, wherein:

said gating means comprise a plurality of gate circuits including a third gate circuit connected to said third comparator circuit, and a fourth gate circuit connected to said first comparator circuit and to said second threshold comparator, said fourth gate circuit being selectively operated to cause said update signal to occur when said first and third comparator circuits and said second threshold comparator all provide output signals.

4. In a pulse code modulated communication system as claimed in claim 1, wherein:

said gating means comprise a plurality of gates including a fifth gate circuit connected to said first and third comparators and to said first threshold comparator and selectively operated to cause the signal update to occur when said first and third comparators and said first threshold comparator all provide output signals.

5. In a pulse code modulated communication system as claimed in claim 2, wherein:

said gating means comprise a plurality of gate circuits including a third gate circuit connected to said third comparator circuit, and a fourth gate circuit connected to said first comparator circuit and to said second threshold comparator, said fourth gate circuit being selectively operated to cause said update signal to occur when said first and third comparator circuits and said second threshold comparator all provide output signals.

6. In a pulse code modulated communication system as claimed in claim 3, wherein:

said gating means comprise a plurality of gates including a fifth gate circuit connected to said first and third comparators and to said first threshold comparator and selectively operated to cause the signal update to occur when said first and third comparators and said first threshold comparator all provide output signals.

7. In a pulse code modulated communication system, as claimed in claim 1, further comprising means connected to said first and second threshold comparators for providing a variable threshold.