Signal scrambler-unscrambler for binary coded transmission system

• US 4,176,247 A
• Filed: 10/10/1973
• Issued: 11/27/1979
• Est. Priority Date: 10/10/1973
• Status: Expired due to Term

• Current Assignee: Sperry Rand Corporation
• Original Assignee: Sperry Rand Corporation
• Inventors: Englund, Robert M.
• Primary Examiner(s): Birmiel, Howard A.
• Application Number:
  US05/405,219
• Time in Patent Office: 2,239 Days
• Field of Search: 178/22, 325/32
• US Class Current: 380/264
• CPC Class Codes: H04L 9/00 Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols

Abstract

A method and an apparatus for encoding and decoding a binary digital data signal is disclosed. An input signal that is to be encoded for transmission is shifted through a serial shift register with the bits in the stages of the shift register at each of the successive shift periods being used to define a binary coded addressable location in an associated memory. The memory has stored in each of its addressable locations a further binary code that when addressed by the shift register produces, as an output, a binary True or Complement signal which through a True/Complement generator couples the True or the Complement of the input signal to the transmission medium. The receiving end of the transmission medium has a similar arrangement of shift register, memory and True/Complement generator that decodes the received encoded transmitted signal.

Claims

1. In a transmission system of a binary digital signal, a signal scrambler comprising:

a shift register having a plurality of bit positions;

a memory having a plurality of addressable locations for storing the alternative True state or Complement state in each of said addressable locations, each of said stored True or Complement states generating a corresponding True or Complement output when selected by said shift register;

means responsively coupling said memory to said shift register for selecting one of said addressable locations;

a True/Complement generator;

a node A for receiving an uncoded input signal of alternative binary digits of 0 or 1;

a node B for emitting an encoded transmitted signal of alternative binary digits of 0 or 1;

means coupling said node A to a first bit position of said shift register;

means coupling said node A to said True/Complement generator;

means coupling the True or Complement output of said memory to said True/Complement generator;

means coupling a second bit position of said shift register to said True/Complement generator for forcing said True/Complement generator to couple the True of said uncoded input signal to said node B until said second bit position receives its initial 1 bit from said node A and thereafter forcing said True/Complement generator to couple the True or the Complement of said uncoded input signal to said node B under control of the True or the Complement output of the memory addressable location that is selected by said shift register.

2. In a transmission system of a binary digital signal, a signal unscrambler comprising:

a shift register having a plurality of bit positions;

a memory having a plurality of addressable locations for storing the alternative True state or Complement state in each of said addressable locations, each of said stored True or Complement states generating a corresponding True or Complement output when selected by said shift register;

means responsively coupling said memory to said shift register for selecting one of said addresses;

a True/Complement generator;

a node B for receiving an encoded transmitted signal of alternative binary digits of 0 or 1;

a node C for emitting a decoded output signal of alternative binary digits of 0 or 1;

means coupling said node C to a first bit position of said shift register;

means coupling said node B to said True/Complement generator;

means coupling the True or Complement output of said memory to said True/Complement generator;

means coupling a second bit position of said shift register to said True/Complement generator for forcing said True/Complement generator to couple the True of said encoded transmitted signal to said node C until said second bit position receives its initial 1 bit from said node C and thereafter forcing said True/Complement generator to couple the True or the Complement of said encoded transmitted signal to said node C under control of the True or the Complement output of the memory addressable that is selected by said serial shift register.

3. In a transmission system of a binary digital signal, a signal scrambler comprising:

a serial shift register of n bits in length having the bit positions 2^n-1, 2^n-2, . . . 2⁰ ;

a decoder;

means coupling the bit positions 2^n-1, 2^n-2, . . . 2⁰ of said serial shift register to said decoder;

a memory having 2ⁿ addressable locations for storing a True state in (2ⁿ /2) of said 2ⁿ addressable locations and a Complement state in the other (2ⁿ /2) of said 2ⁿ addressable locations;

means coupling the decoded output of said decoder to said memory for selecting only one of said 2ⁿ addressable locations as determined by the bits in the bit positions 2^n-1, 2^n-2, . . . 2⁰ of said shift register;

a node A for receiving an uncoded input signal of alternative binary digits of 0 or 1;

a node B for emitting an encoded transmitted signal of alternative binary digits of 0 to 1;

means coupling said node A to the bit position 2^n-1 of said serial shift register;

a True/Complement generator comprising;

an inverter;

means coupling the bit position 2⁰ of said serial shift register to the input of said inverter;

a first Flip-Flop having a P input and a Q output;

means coupling the output of said inverter to the P input of said first Flip-Flop;

an AND gate;

means coupling the Q output of said first Flip-Flop as a first input to said AND gate;

a second Flip-Flop having a D input and a Q output;

means coupling the True or Complement output of said memory to the D input of said second Flip-Flop;

means coupling the Q output of said second Flip-Flip as the second input to said AND gate;

and Exclusive OR gate;

means coupling said uncoded input signal at said node A as the first input to said Exclusive OR gate;

means coupling the output of said AND gate as the second input to said Exclusive OR gate;

a third Flip-Flop having a D input and a Q output;

means coupling the output of said Exclusive OR gate to the D input of said third Flip-Flop;

means coupling the Q output of said third Flip-Flop to said node B;

the bit in the bit position 2⁰ of said serial shift register forcing said True/Complement generator to couple the True of said uncoded input signal to said node B until the bit position 2⁰ of said serial shift register receives its initial 1 bit from said node A and thereafter forcing said True/Complement generator to couple the True or the Complement of said uncoded input signal to said node B under control of the True or the Complement content of the addressable location selected by said decoder and the contents of the bit positions 2^n-1, 2^n-2, . . . 2⁰ of said serial shift register.

4. In a transmission system of a binary digital signal, a signal unscrambler comprising:

a serial shift register of n bits in length having the bit positions 2^n-1, 2^n-2, . . . 2⁰ ;

a decoder;

means coupling the bit positions 2^n-1, 2^n-2, . . . 2⁰ of said serial shift register to said decoder;

a memory having 2ⁿ addressable locations for storing a True state in (2ⁿ /2) of said 2ⁿ addressable locations and a Complement state in the other (2ⁿ /2) of said 2ⁿ addressable locations;

means coupling the decoded output of said decoder to said memory for selecting only one of said 2ⁿ addressable locations as determined by the bits in the bit positions 2^n-1, 2^n-2, . . . 2⁰ of said shift register;

a node B for receiving an encoded transmitted signal of alternative binary digits of 0 or 1;

a node C for emitting a decoded output signal of alternative binary digits of 0 or 1;

means coupling said node C to the bit position 2^n-1 of said serial shift register;

a True/Complement generator comprising;

an inverter;

means coupling the bit position 2⁰ of said serial shift register to the input of said inverter;

a first Flip-Flop having a P input and a Q output;

means coupling the output of said inverter to the P input of said first Flip-Flop;

an AND gate;

means coupling the Q output of said first Flip-Flop as a first input to said AND gate;

a second Flip-Flop having a D input and a Q output;

means coupling the True or Complement output of said memory to the D input of said second Flip-Flop;

means coupling the Q output of said second Flip-Flop as the second input to said AND gate;

an Exclusive OR gate;

means coupling said encoded transmitted signal at said node B as the first input to said Exclusive OR gate;

means coupling the output of said AND gate as the second input to said Exclusive OR gate;

a third Flip-Flop having a D input and a Q output;

means coupling the output of said Exclusive OR gate to the D input of said third Flip-Flop;

means coupling the Q output of said third Flip-Flop to said node C;

the bit in the bit position 2⁰ of said serial shift register forcing said True/Complement generator to couple the True of said encoded transmitted signal to said node C until the bit position 2⁰ of said serial shift register receives its initial 1 bit from said node C and thereafter forcing said True/Complement generator to couple the True or the Complement of said encoded transmitted signal to said node C under control of the True or the Complement content of the addressable location selected by said decoder and the contents of the bit positions 2^n-1, 2^n-2, . . . 2⁰ of said serial shift register.

5. In a transmission system of a binary digital signal, a signal scrambler/unscrambler comprising:

a node A for receiving an uncoded input signal;

an encoding transmitter and a decoding receiver coupled by a transmission medium;

said encoding transmitter comprising;

a serial shift register of n bits in length having the bit positions 2^n-1, 2^n-2, . . . 2⁰, and responsively coupled to said node A for storing the bits of said uncoded input signal therein;

a memory having 2ⁿ addressable locations for storing the alternative True or Complement state in each of said 2ⁿ addressable locations;

a decoder coupled to the bit positions 2^n-1, 2^n-2, . . . 2⁰ of said serial shift register and to said memory for decoding the binary coded word formed by the bits of said uncoded input signal stored in the respective bit positions 2^n-1, 2^n-2, . . . 2⁰ of said serial shift register and selecting the one addressable location in said memory as determined by said binary coded word, said one selected addressable location generating an associated True or Complement output;

a True/Complement generator including means responsively coupled to the bit position 2⁰ of said serial shift register, to the True or Complement output of said memory and to said uncoded input signal at said node A for coupling the True of said uncoded input signal to said transmission medium until the bit position 2⁰ of said serial shift register receives its initial 1 bit of said uncoded input signal and thereafter coupling the True or the Complement of said uncoded input signal to said transmission medium when effected by said True or Complement output of said memory.

6. In the transmission system of claim 5, said decoding receiver comprising:

a node C for emitting a decoded output signal that is identical to said uncoded input signal;

a serial shift register of n bits in length having the bit positions 2^n-1, 2^n-2, . . . 2⁰, and responsively coupled to said node C for storing the bits of said decoded output signal therein;

a memory having 2ⁿ addressable locations for storing the alternative True or Complement state in each of said 2ⁿ addressable locations;

a decoder coupled to the bit positions 2^n-1, 2^n-2, . . . 2⁰ of said serial shift register and to said memory for decoding the binary coded word formed by the bits of the decoded output signal stored in the respective bit positions 2^n-1, 2^n-2, . . . 2⁰ of said serial shift register and selecting the one addressable location in said memory as determined by said binary coded word, said one selected addressable location generating an associated True or Complement output;

a True/Complement generator including means responsively coupled to the bit position 2⁰ of said serial shift register;

to the True or Complement output of said memory and to said encoded transmitted signal on said transmission medium for coupling the True of said encoded transmitted signal to said node C until the bit position 2⁰ of said serial shift register receives its initial 1 bit of said encoded transmitted signal and thereafter coupling the True or the Complement of said encoded transmitted signal to said node C when effected by said True or Complement output of said memory.

7. In a transmission system of a binary digital signal, a signal scrambler comprising:

a serial shift register of n bits in length having the bit positions 2^n-1, 2^n-2, . . . 2⁰ ;

a decoder;

means coupling the bit positions 2^n-1, 2^n-2, . . . 2⁰ of said serial shift register to said decoder;

a memory having 2ⁿ addressable locations for storing the alternative True state or Complement state in said 2ⁿ addressable locations;

means coupling the decoded output of said decoder to said memory for selecting one of said 2ⁿ addressable locations as determined by the bits in the bit positions 2^n-1, 2^n-2, . . . 2⁰ of said shift register, said selected one addressable location generating a True or a Complement output;

a True/Complement generator;

a node A for receiving an uncoded input signal of continuous alternative binary digits of 0 or 1;

a node B for emitting an encoded transmitted signal of continuous alternative binary digits of 0 or 1;

means coupling said node A to the bit position 2^n-1 of said shift register;

means coupling said node A to said True/Complement generator;

means coupling the True or the Complement output of said memory to said True/Complement generator;

means coupling the bit position 2⁰ of said serial shift register to said True/Complement generator for forcing said True/Complement generator to couple the True of said uncoded input signal to said node B until the bit position 2⁰ of said shift register receives its initial 1 bit from said node A and thereafter forcing said True/Complement generator to couple the True or the Complement of said uncoded input signal to said node B under control of the changing True or Complement outputs of the addressable locations that are selected by said decoder and the changing contents of the bit positions 2^n-1, 2^n-2, . . . 2⁰ of said serial shift register as said uncoded input signal sequentially shifts through said shift register in the ordered bit positions 2^n-1, 2^n-2, . . . 2⁰.

8. In a transmission system of a binary digital signal, a signal scrambler comprising:

a serial shift register of n bits in length having the bit positions 2^n-1, 2^n-2, . . . 2⁰ ;

a decoder;

means coupling the bit positions 2^n-1, 2^n-2, . . . 2⁰ of said serial shift register to said decoder;

a memory having 2ⁿ addressable locations for storing the alternative True or Complement state in each of said 2ⁿ addressable locations, each of said stored True or Complement states generating a corresponding True or Complement output when selected by said decoder;

means coupling the decoded output of said decoder to said memory for selecting only one of said 2ⁿ addressable locations as determined by the bits in the bit positions 2^n-1, 2^n-2, . . . 2⁰ of said shift register;

a True/Complement generator;

a node A for receiving an uncoded input signal of alternative binary digits of 0 or 1;

a node B for emitting an encoded transmitted signal of alternative binary digits of 0 or 1;

means coupling said node A to the bit position 2^n-1 of said shift register;

means coupling said node A to said True/Complement generator;

means coupling the True or the Complement output of said memory to said True/Complement generator;

means coupling only the bit position 2⁰ of said shift register to said True/Complement generator for forcing said True/Complement generator to couple the True of said uncoded input signal to said node B until the bit position 2⁰ of said shift register receives its initial 1 bit from said node A and thereafter forcing said True/Complement generator to couple the True or the Complement of said uncoded input signal to said node B under control of the True or the Complement output of the addressable location selected by said decoder and the contents of the bit positions 2^n-1, 2^n-2, . . . 2⁰ of said serial shift register.

9. In a transmission system of a binary digital signal, a signal unscrambler comprising:

a serial shift register of n bits in length having the bit positions 2^n-1, 2^n-2, . . . 2⁰ ;

a decoder;

means coupling the bit positions 2^n-1, 2^n-2, . . . 2⁰ of said serial shift register to said decoder;

a memory having 2ⁿ addressable locations for storing the alternative True or Complement state in each of said 2ⁿ addressable locations, each of said stored True or Complement states generating a corresponding True or Complement output when selected by said decoder;

means coupling the decoded output of said decoder to said memory for selecting only one of said 2ⁿ addressable locations as determined by the bits in the bit positions 2^n-1, 2^n-2, . . . 2⁰ of said serial shift register;

a True/Complement generator;

a node B for receiving an encoded transmitted signal of alternative binary digits of 0 or 1;

a node C for emitting a decoded output signal of alternative binary digits of 0 or 1;

means coupling said node C to the bit position 2^n-1 of said shift register;

means coupling said node B to said True/Complement generator;

means coupling the True or the Complement output of said memory to said True/Complement generator;

means coupling only the bit position 2⁰ of said serial shift register to said True/Component generator for forcing said True/Complement generator to couple the True of said encoded transmitted signal to said node C until the bit position 2⁰ of said serial shift register receives its initial 1 bit from said node C and therafter forcing said True/Complement generator to couple the True or the Complement of said encoded transmitted signal to said node C under control of the True or the Complement output of the addressable location selected by said decoder and the contents of the bit positions 2^n-1, 2^n-2, . . . 2⁰ of said serial shift register.

10. In a transmission system of a binary digital signal:

a node A for receiving an uncoded input signal of alternative binary digits of 0 or 1;

an inverter;

register means for coupling said uncoded input signal from said node A to the input of said inverter;

a first Flip-Flop having a plurality of inputs and outputs;

means for coupling the output of said inverter to a first input of said first Flip-Flop;

an AND gate;

means for coupling a first output of said first Flip-Flop as a first input to said AND gate;

a second Flip-Flop having a plurality of inputs and outputs;

means responsively coupled to said register means for generating a True or a Complement output signal;

means for coupling said True or Complement output signal as a first input to said second Flip-Flop;

means for coupling a first output of said second Flip-Flop as the second input to said AND gate;

an Exclusive OR gate;

means for coupling said uncoded input signal at said node A as the first input to said Exclusive OR gate;

means for coupling the output of said AND gate as the second input to said Exclusive OR gate;

a third Flip-Flop having a plurality of inputs and outputs;

means for coupling the output of said Exclusive OR gate to a first input of said third Flip-Flop;

a node B for emitting an encoded transmitted signal of alternative binary digits of 0 or 1;

means for coupling a first output of said third Flip-Flop to said node B;

said uncoded input signal at said inverter disabling said AND gate for forcing said Exclusive OR gate to couple the True of said uncoded input signal to said node B until the initial 1 bit of said uncoded input signal at said inverter enables said AND gate for coupling the True or the Complement of said uncoded input signal to said node B when said Exclusive OR gate is effected by said True or Complement output signal, respectively.

11. In a transmission system of a binary digital signal:

a node B for receiving an encoded transmitted signal of alternative binary digits of 0 to 1;

a node C for emitting a decoded output signal of alternative binary digits of 0 L to 1;

an inverter;

register means for coupling said decoded output signal from said node C to the input of said inverter;

a first Flip-Flop having a plurality of inputs and outputs;

means for coupling the output of said inverter to a first input of said first Flip-Flop;

an AND gate;

means for coupling a first output of said first Flip-Flop as a first input to said AND gate;

a second Flip-Flop having a plurality of inputs and outputs;

means responsively coupled to said register means for generating a True or a Complement output signal;

means for coupling said True or Complement output signal as a first input to said second Flip-Flop;

means for coupling a first output of said second Flip-Flop as the second input to said AND gate;

an Exclusive OR gate;

means for coupling said encoded transmitted signal at said node B as the first input to said Exclusive OR gate;

means for coupling the output of said AND gate as the second input to said Exclusive OR gate;

a third Flip-Flop having a plurality of inputs and outputs;

means for coupling the output of said Exclusive OR gate to a first input of said third Flip-Flop;

means for coupling a first output of said third Flip-Flop to said node C;

said decoded output signal from said node C and said register means at said inverter disabling said AND gate for forcing said Exclusive OR gate to couple the True of said encoded transmitted signal to said node C until the initial 1 bit of said decoded output signal from said node C and said register means at said inverter enables said AND gate for coupling the True or the Complement of said encoded transmitted signal to said node C when said Exclusive OR gate is effected by said True or Complement output signal, respectively.