Liquid crystal display device using signal converter of digital type

• US 4,180,813 A
• Filed: 07/26/1977
• Issued: 12/25/1979
• Est. Priority Date: 07/26/1977
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Yoneda, Yutaka
• Primary Examiner(s): Trafton, David L.
• Application Number:
  US05/819,408
• Time in Patent Office: 882 Days
• Field of Search: 340/324 M, 340/784, 358/240, 358/241, 358/283, 350/333
• US Class Current: 345/100
• CPC Class Codes: G09G 3/2007 Display of intermediate tones
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/3622 using a passive matrix G09G3/3674 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3674 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3685 Details of drivers for data electrodes
• CPC Class Codes: H04N 3/127 using liquid crystals

Abstract

A liquid crystal display device capable of displaying halftone pictures comprises a liquid crystal display panel in which liquid crystal picture elements are provided at the intersections of the m scanning electrodes and the n signal electrodes arranged in matrix configuration so as to be selectively lit up, a first liquid crystal drive circuit for selectively applying scanning voltages to the m scanning electrodes, a second liquid crystal drive circuit for applying brightness signal voltages to the n signal electrodes, wherein the signal converting circuit for supplying the n brightness signal voltages corresponding to the n signal electrodes to the second liquid crystal drive circuit in synchronism with the scanning voltages is simplified by constructing all the component circuits, except the A/D converter, in digital fashion so that it can be easily integrated and that every signal electrode need not be provided with a brightness control circuit.

Claims

1. A liquid crystal display device for displaying a video signal, comprising:

(a) a liquid crystal display panel in which liquid crystal picture elements are located at intersections of plural rows of scanning electrodes and plural columns of signal electrodes arranged in a matrix configuration, the transmissivity of said liquid crystal picture elements being selectively controlled when the associated scanning and signal electrodes are energized;

(b) a control circuit for generating a first, a second, and a third clock signal;

(c) ring counter means for producing a scanning signal in response to said first clock signal;

(d) means for energizing selected ones of said scanning electrodes in response to said scanning signal;

(e) a signal electrode drive circuit including a plurality of drivers, each of said drivers being connected to one of said electrodes for energizing the same; and

(f) a signal converting circuit including;

an analog-to-digital converter for converting a video signal to be displayed for one horizontal period into a plurality of time-serial binary-coded signals each corresponding to an amplitude of a corresponding part of said video signal;

means for converting said plurality of time-serial binary-coded signals into a plurality of time-serial pulse trains in accordance with said second clock signal, each train including a number of pulses determined by the corresponding binary-coded signal;

a plurality of first shift registers connected in series for storing said plurality of time-serial pulse trains; and

a plurality of second shift registers, each first shift register being connected to one of said second shift registers, for storing the contents of said first shift registers at a time in response to said first clock signal and, each of said second shift registers being connected to one of said drivers correspondingly and respectively, for supplying said time-serial pulse trains to the same in accordance with said third clock signal.

2. A liquid crystal display device for displaying a video signal, comprising:

(a) a liquid crystal display panel in which liquid crystal picture elements are located at intersections of plural rows of scanning electrodes and plural columns of signal electrodes arranged in a matrix configuration, the transmissivity of said liquid crystal picture elements being selectively controlled when the associated scanning and signal electrodes are energized;

(b) a control circuit for generating a first, a second, and a third clock signal;

(c) ring counter means for producing a scanning signal in response to said first clock signal;

(d) means for energizing selected ones of said scanning electrodes in response to said scanning signal;

(e) a signal electrode drive circuit including a plurality of drivers, each of said drivers being connected to one of said electrodes for energizing the same; and

(f) a signal converting circuit including;

an analog-to-digital converter for converting a video signal to be displayed for one horizontal period into a plurality of time-serial binary-coded signals each corresponding to an amplitude of a corresponding part of said video signal;

means for converting said plurality of time-serial binary-coded signals into a plurality of time-serial pulse trains in accordance with said second clock signal, each train including a number of pulses determined by the corresponding binary-coded signal;

a plurality of first shift registers connected in series and coupled to selectively receive a plurality of time-serial pulse trains from said converting means;

a plurality of second shift registers connected in series and being coupled to selectively receive a plurality of time-serial pulse trains from said converting means; and

changeover switch means, coupled to said pluralities of first and second shift registers, for alternately coupling said second clock signal thereto, and thereby alternately causing the storage of successive pluralities of time-serial pulse trains into said pluralities of first and second shift registers, respectively, and for alternately coupling said third clock signal thereto, and thereby alternately causing the contents of said pluralities of said second and first shift registers, respectively, to be applied to corresponding ones of the plurality of drivers of said signal electrode drive circuit.

3. A liquid crystal display device for displaying a video signal, comprising:

(a) a liquid crystal display panel in which liquid crystal picture elements are located at intersections of plural rows of scanning electrodes and plural columns of n signal electrodes arranged in a matrix configuration, the transmissivity of said liquid crystal picture elements being selectively controlled when the associated scanning and signal electrodes are energized;

(b) a control circuit for generating a first, a second, and a third clock signal;

(c) ring counter means for producing a scanning signal in response to said first clock signal;

(d) means for energizing selected ones of said scanning electrodes in response to said scanning signal;

(e) a signal electrode drive circuit including a plurality of drivers, each of said drivers being connected to one of said electrodes for energizing the same; and

(f) a signal converting circuit including;

an analog-to-digital converter for converting a video signal to be displayed for one horizontal period into a plurality of time-serial binary-coded signals each corresponding to an amplitude of a corresponding part of said video signal;

means for converting said plurality of time-serial binary-coded signals into a plurality of time-serial pulse trains in accordance with said second clock signal, each train including a number of pulses determined by the corresponding binary-coded signal;

a plurality (n+1) of first shift registers connected in series, each having a capacity of N bits and being coupled to selectively receive a plurality of time-serial pulse trains from said converting means;

a plurality (n+1) of second shift registers connected in series, each having a capacity of N bits and being coupled to selectively receive a plurality of time-serial pulse trains from said converting means;

a plurality n of first output terminals;

a plurality n of second output terminals;

a plurality n of first inverters coupled to the outputs of the second to (n+1)th first shift registers;

a plurality n of second inverters coupled to the outputs of the second to (n+1)th second shift registers;

first changeover switch means, coupled to said pluralities of first and second output terminals and said pluralities of first and second shift registers, for alternately connecting the output of the k-th shift register and the output of the (k+1)-th shift register to each of said first and second pluralities of shift registers to the k-th output terminal of said pluralities of first and second output terminals, respectively, each time the contents of said pluralities of shift registers are shifted by N bits, K being 1, 2, 3, . . . n+1; and

second changeover switch means, coupled to said pluralities of first and second output terminals, for alternately connecting the n output terminals of said pluralities of first and second output terminals, to corresponding ones of the plurality of drivers of said signal electrode drive circuit, in response to said third clock signal.