Cardiotachometer

• US 4,181,134 A
• Filed: 09/21/1977
• Issued: 01/01/1980
• Est. Priority Date: 09/21/1977
• Status: Expired due to Term

• Current Assignee: John D. Petronis, Richard C. Mason
• Original Assignee: John D. Petronis, Richard C. Mason
• Inventors: Petronis, John D., Mason, Richard C.
• Primary Examiner(s): Michell, Robert W.
• Assistant Examiner(s): Tayon, Jeffrey W.
• Application Number:
  US05/835,478
• Time in Patent Office: 832 Days
• Field of Search: 128/2.05 P, 128/2.05 T, 128/2.06 F, 128/2.06 A, 128/2.06 B, 128/2.06 G, 128/2.06 R, 307/229, 307/230, 307/236, 340/347 NT, 324/780, 328/127, 328/129
• US Class Current: 600/502
• CPC Class Codes: A61B 5/02438 with portable devices, e.g. worn by the patient
• CPC Class Codes: A61B 5/332 Portable devices specially adapted therefor
• CPC Class Codes: A61B 5/6831 Straps, bands or harnesses

Abstract

A cardiotachometer includes features which reliably filter out interfering background signals and provide for relatively low power consumption. A differential amplifier is connected to a three electrode input so as to effectively reduce common mode errors. The output of the differential amplifier is connected to an automatic polarity selecting circuit and an automatic gain control amplifier so as to make the unit as independent as possible from user adjustment. The device includes an eight bear counter for producing a single output pulse for every eight input pulses. The output of the eight beat counter is connected to a dual slope analog-to-digital converter for developing a display which is directly related to the average heart rate over a eight beat period and inversely related to the voltage applied to the circuit. A low power liquid crystal display is connected to the output of the dual slope circuit.

Claims

1. A cardiotachometer apparatus comprising:

a pick-up means for picking up electrical signals from heart beats;

an initial signal processing means having an input connected to said pick-up means and an output, said initial signal processing means including an amplifier means therein;

a signal recognizing means having an input connected to the output of said initial signal processing means, said signal recognizing means including a heart beat counter means for counting said heart beats and producing an output once for every Nth heart beat, N being equal to or greater than 2, said output occuring at intervals T apart;

a reciprocal generating means for producing an output directly proportional to 1/T, said reciprocal generating means including;

a ramp generator having an input and an output, the input of said ramp generator being connected to the output of said signal recognizing means;

a sample-and-hold means having at least two inputs and one output, one of said sample-and-hold inputs being connected to the output of said ramp generator and one of said other inputs of said sample-and-hold generator being connected to the output of said signal recognizing means; and

,

a ratiometric dual/slope analog-to-digital conversion means having at least two inputs and one output, at least one of said inputs to said ratiometric dual/slope analog-to-digital conversion means being connected to the output of said sample-and-hold means and at least one of the other of said inputs of said ratiometric dual/slope analog-to-digital conversion means being connected to the output of said signal recognizing means; and

,

a display means for producing a visual output, said display means being connected to said reciprocal generating means, the output of said display means being directly proportional to the heart beat rate between outputs of said counter means.

2. The apparatus of claim 1 further including:

an automatic polarity selecting circuit means included in said initial signal processing means for producing an output of specified polarity in response to an input of either positive or negative polarity.

3. The apparatus of claim 1 further including:

a common mode rejection means incorporated in said initial signal processing means.

4. The apparatus of claim 3 wherein said common mode rejection means comprises a differential amplifier.

5. The apparatus of claim 4 wherein said pick-up means comprises a three electrode system.

6. The apparatus of claim 1 wherein said initial signal processing means comprises:

a differential amplifier having an input and an output, the input of said differential amplifier being connected to said pick-up means;

a bandpass filter having an input and an output, the input of said bandpass filter being connected to the output of said differential amplifier;

an automatic polarity selector having an input and an output, the input of said automatic polarity selector being connected to the output of said bandpass filter; and

,

an automatic gain control amplifier having an input and an output, the input of said automatic gain control amplifier being connected to the output of said automatic polarity selector.

7. The apparatus of claim 1 wherein said signal recognizing means comprises:

a threshhold detector having an input and an output, the input of said threshhold detector being connected to the output of said initial signal processing means;

a monostable circuit having an input and an output, the input of said monostable circuit being connected to the output of said threshhold detector;

an Nth beat counter means having an input and an output, the input of said Nth beat counter means being connected to the output of said monostable circuit; and

,

a timing pulse generator having an input and an output, the input of said timing pulse generator being connected to the output of said Nth beat counter.

8. The apparatus of claim 6 wherein said signal recognizing means comprises:

a threshhold detector having an input and an output, the input of said threshhold detector being connected to the output of said initial signal processing means;

a monostable circuit having an input and an output, the input of said monostable circuit being connected to the output of said threshhold detector;

an Nth beat counter means having an input and an output, the input of said Nth beat counter means being connected to the output of said monostable circuit; and

,

a timing pulse generator having an input and an output, the input of said timing pulse generator being connected to the output of said Nth beat counter.

9. The apparatus of claim 8 wherein said display means comprises:

a liquid crystal display.

10. The apparatus of claim 9 wherein said Nth beat counter produces one output pulse for every eight input pulses.

11. The apparatus of claim 1 wherein said dual/slope analog-to-digital conversion means comprises:

a counter means;

a clock means connected to said counter means;

a first means for activating said counter means until it reaches a predetermined count;

a switch means connected to said counter means and activated by said counter means when said counter means reaches said predetermined count; and

,

a second means connected to said switch means for reactivating said counter means after said predetermined count has been made.

12. The apparatus of claim 11 further comprising:

an integrator means having the input thereof connected to said first and second means and the output thereof connected to said counter means.

13. The apparatus of claim 12 wherein said switch means comprises a flip-flop circuit.

14. The apparatus of claim 13 further comprising:

a high speed comparator means and a voltage level shifting means connected between the output of said integrator means and the input of said counter means.

15. The apparatus of claim 14 wherein said flip-flop means includes a first and a second output terminals, said first and second output terminals being the inverse of each other;

and,

wherein said first and said second means includes field effect transistor switch means therein having the input gates thereof respectively connected to the first and second output terminals of said flip-flop.