Memory access and sharing control system
First Claim
1. In a system having a random access memory means with a number of addressable locations, a group of low priority memory users and at least one high priority memory user and a memory controller which is operatively connected with the memory means and which is further connected with all of said users by means of a first data and control bus, each memory user including means to provide memory access signals to the memory controller to cause data to be transferred to or from the memory means;
- the improvement comprising;
a second data bus;
means for signalling that the memory access signals provided by the high priority user require a block transfer operation involving multiple memory accesses for a block of data; and
the memory controller including;
a timing generator for generating a set of timing signals;
means responsive to said signalling means and to said timing signal set for generating a set of high priority timing signals including a high priority time signal which is periodic from the start to the completion of such a transfer of a block of data; and
means responsive to the high priority time signal to access thememory means with the memory access signals of the high priority memory user during one half of the period of the high priority time signal and to transfer the accessed data to the high priority memory user via the second data bus and to access the memory means with the memory access signals of the low priority memory users (1) during the other half of the period of the high priority time signal and (2) during such time that the high priority time signal is not periodic and to transfer the data so accessed to such low priority memory users via the first data and control bus.
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Accused Products
Abstract
An apparatus and arrangement is disclosed for controlling the sharing of an electronic memory between a number of memory users, at least one of which requires transfers of blocks of data on a high priority basis. Access to the memory is controlled by means of a modified time division multiplexing scheme whereby a set of time slots is assigned for performing memory accesses requested by high priority memory users, but, during times in which no high priority users are using the memory, these time slots may be used by other memory users in the order of pre-assigned priorities. Independent output data paths are provided for the respective high and low priority data transfers.
28 Citations
5 Claims
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1. In a system having a random access memory means with a number of addressable locations, a group of low priority memory users and at least one high priority memory user and a memory controller which is operatively connected with the memory means and which is further connected with all of said users by means of a first data and control bus, each memory user including means to provide memory access signals to the memory controller to cause data to be transferred to or from the memory means;
- the improvement comprising;
a second data bus; means for signalling that the memory access signals provided by the high priority user require a block transfer operation involving multiple memory accesses for a block of data; and the memory controller including; a timing generator for generating a set of timing signals; means responsive to said signalling means and to said timing signal set for generating a set of high priority timing signals including a high priority time signal which is periodic from the start to the completion of such a transfer of a block of data; and
means responsive to the high priority time signal to access thememory means with the memory access signals of the high priority memory user during one half of the period of the high priority time signal and to transfer the accessed data to the high priority memory user via the second data bus and to access the memory means with the memory access signals of the low priority memory users (1) during the other half of the period of the high priority time signal and (2) during such time that the high priority time signal is not periodic and to transfer the data so accessed to such low priority memory users via the first data and control bus. - View Dependent Claims (2, 3, 4, 5)
- the improvement comprising;
Specification