Multiprocessor for providing fault isolation test upon itself

• US 4,181,940 A
• Filed: 02/28/1978
• Issued: 01/01/1980
• Est. Priority Date: 02/28/1978
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Westinghouse Electric Corporation (Paramount Global (f/k/a ViacomCBS Inc.))
• Inventors: Underwood, Thomas E., Holden, James J. III
• Primary Examiner(s): Malzahn, David H.
• Application Number:
  US05/882,030
• Time in Patent Office: 672 Days
• Field of Search: 364/200, 235/303.4, 235/304
• US Class Current: 714/25
• CPC Class Codes: G06F 11/2242 in multi-processor systems, e.g. one processor becoming the test master G06F11/2736 takes precedence
• CPC Class Codes: G06F 11/277 with comparison between actual response and known fault-free response

Abstract

An improved multiprocessor system for providing fault isolation test upon itself is described incorporating at least a first and second digital processor, a first, second and third memory and means for switching in one memory in place of another. In addition, methods are provided for fault isolation test in a multiprocessor system and for protecting the contents of one or more selected memories.

Claims

1. A multiprocessor system to facilitate fault isolation test upon one of its processors by another comprising:

a first, second, and third memory each having a plurality of memory address locations for storing a plurality of instructions and data;

a first and second digital processor, each said processor operative to execute instructions and operate upon data stored in at least one of said memories, each said processor having an input/output port responsive to control signals including halt, initiate, clear and interrupt commands, and at least one port for transferring data and instructions;

a transfer switch coupled to each of said memories and processors for transferring instructions and data between said memories and said port of said first and second processors, said transfer switch including means for switching said third memory in place of said first memory in response to a memory switching command signal and for causing said first memory at times when replaced by said third memory to be inaccessible by said first and second digital processors to protect the integrity of the information stored in said first memory;

said means for switching includes means for addressing said third memory by an address directed to said third memory and by an address directed to said first memory at times when replaced by said third memory,

said transfer switch including means for protecting the information in said second memory in response to a memory protection command signal while permitting information to be read from said second memory;

an input/output means coupled to said input/output port of said first and second processors for receiving, decoding and generating initiate, halt, clear and interrupt command signals and for receiving and decoding "who am I" identification request, memory switching and memory protection command signals, said input/output means coupled to a control input of said transfer switch for providing memory switching and memory protection command signals.

2. The multiprocessor of claim 1 wherein:

said first and second digital processors each are operative to reset all its registers to zero in response to said clear command signal.

3. The multiprocessor of claim 1 wherein:

said first and second digital processors each are operative to cause an instruction to be fetched and executed in response to said initiate command signal.

4. The multiprocessor of claim 1 wherein:

said first and second digital processors each are operative to halt the fetching and the execution of instructions in response to said halt command signal and operative to fetch and execute one instruction only in response to the presence of both said initiate and halt command signals.

8. The multiprocessor of claim 1 wherein said means for protecting the information in said second memory includes means for inhibiting write operations in said second memory.

9. The multiprocessor of claim 1 wherein:

said first and second digital processors each are operative to execute instructions including add, subtract, load, store, input, output, NAND, conditional branch and shift instructions.

5. A method for performing fault isolation test on a first processor by a second processor within a multiprocessor system including a plurality of processors and a plurality of memories comprising the steps of:

halting and clearing said first processor;

switching in a first memory in place of a second memory for use by said first processor under test, said second memory containing a start-up program for said multiprocessor system;

writing a test program including at least one instruction into said first memory, said test program beginning at a predetermined address;

initiating said first processor including the steps of reading an instruction from said first memory at said predetermined address and executing said instruction;

comparing the data in said first memory in at least one address location with first predetermined data to detect an error indicative of a fault in said first processor;

upon detection of an error, comparing the data in said first memory with additional predetermined data in response to detection of an error to isolate the location of a processor fault capable of causing said error; and

generating a predetermined signal indicative of the location of said fault.

6. A method for performing fault isolation test on a first processor in a multiprocessor system including a plurality of processors and a plurality of memories by a second processor comprising the steps of:

halting and clearing said first processor;

switching in a first memory in place of a second memory for use by said first processor under test, said second memory containing a start-up program for said multiprocessor system;

writing a test program including at least an instruction into said first memory, said test program beginning at a predetermined address;

initiating said first processor including the steps of reading an instruction from said first memory at said predetermined address and executing said instruction;

comparing the data in said first memory in at least one address location with first predetermined data to detect an error indicative of a fault in said first processor;

upon detection of no error, writing another test program including at least an instruction into said first memory;

initiating said first processor including the steps of reading an instruction from said first memory and executing said instruction;

comparing the data in said first memory in at least one address location with second predetermined data to detect an error indicative of a fault in said first processor; and

upon detection of no error, generating a predetermined signal indicative of no fault located.

7. A method for performing fault isolation test on a first processor in a multiprocessor system including a plurality of processors and a plurality of memories by a second processor comprising the steps of:

halting and clearing said first processor;

switching in a first memory in place of a second memory for use by said first processor, said second memory containing a start-up program for said multiprocessor system;

writing a test program into said first memory beginning at a predetermined address;

said test program including at least one instruction;

initiating said first processor including the steps of reading an instruction from said first memory at said predetermined address and executing said instruction;

halting by a control signal from said second processor said first processor after execution of said test program; and

comparing the data in said first memory in at least one address location with first predetermined data to detect an error indicative of a fault in said first processor.