Digital indicia generator employing compressed data

• US 4,181,956 A
• Filed: 11/07/1977
• Issued: 01/01/1980
• Est. Priority Date: 11/07/1977
• Status: Expired due to Term

• Current Assignee: Cardion, Inc.
• Original Assignee: General Signal Corporation (SPX Corporation)
• Inventors: Rost, David P., Schwab, Carl E.
• Primary Examiner(s): Gruber, Felix D.
• Application Number:
  US05/849,143
• Time in Patent Office: 785 Days
• Field of Search: 364/521, 364/720, 315/365, 315/367, 346/1, 346/34, 340/725, 340/747, 340/750, 340/745, 340/722, 340/728, 340/799, 340/800, 340/803
• US Class Current: 345/443
• CPC Class Codes: G09G 1/18 a small local pattern covering only a single character, and stepping to a position for the following character, e.g. in rectangular or polar co-ordinates, or in the form of a framed star
• CPC Class Codes: G09G 5/42 characterised by the display of patterns using a display memory without fixed position correspondence between the display memory contents and the display position on the screen

Abstract

A display indicia generator driven by compressed data is arranged to draw indicia on a display coordinated with signals from an external environment. For drawing a line, for example, the compressed data includes coordinates of a point on the line, a slope of the line and a length of the line. The display includes a deflection system for deflecting a writing beam, such as a cathode ray beam, over the display area in a predetermined pattern, i.e., a raster scan or PPI display. The signal source for the external signals to be displayed is coupled via a mixer to the unblanking control of the display. Another input to the mixer comes from the indicia generator which is arranged to enable the beam when it reaches a point, such as the start point on the line. On each succeeding coordinate scan, counters keep track of the portion of the sweep during which the beam should be unblanked so as to display the line. At the completion of the frame, the indicia has been generated concurrently with the signals. Both raster scan and PPI scan embodiments are disclosed.

Claims

1. In a display system for displaying signals representing an environment external thereto, said display system including a CRT display with a deflection means for sweeping a cathode ray beam over said CRT display in a predetermined pattern with means for controlling unblanking of said beam for creating visible manifestations on said CRT display, an indicia generator for providing signals to said means for controlling unblanking of said beam to write indicia on said CRT display concurrently with manifestations of said environmental signals and coordinated therewith in which said indicia generator is driven by data in compressed form comprising:

storage means for storing parameters related to said indicia including coordinates of a point on said indicia, a slope for said indicia and a length for said indicia, and

first means responsive to said stored parameters and to beam position in said pattern for producing signals to control unblanking of said beam to write indicia corresponding to said stored parameters.

2. The apparatus of claim 1 wherein said first means includes arithmetic means responsive to said stored parameters for computing coordinates of said indicia other than said stored coordinates.

3. The apparatus of claim 2 in which said deflection means sweeps said beam in a pattern in Cartesian coordinate system.

4. The apparatus of claim 2 in which said deflection means sweeps said beam in a pattern in a polar coordinate system.

5. The apparatus of claim 2 in which said indicia generator is capable of displaying multiple overlapping indicia and in which:

said storage means stores for each of said multiple indicia coordinates of a point on each of said indicia, a slope and length for said indicia, said apparatus further including

means including plural scratch pad memories coupled to said arithmetic means to store data representing intersections of indicia with a succeeding scan of said deflection means,

said plural scratch pad memories including read out circuits driven by said deflection means for readout synchronous with beam deflection.

6. The apparatus of claim 5 which further includes scratch pad memory control means for selectively and sequentially enabling scratch pad reading, writing and clearing of each of said scratch pad memories.

7. The apparatus of claim 5 in which said storage means stores slope data as a first derivative of said indicia with respect to one coordinate of said deflection sweep, and in which said arithmetic means modifies at least one stored coordinate of said indicia by use of said slope.

8. The apparatus of claim 5 in which said first means also includes:

a further memory with storage for range, slope and span data for plural indicia,

means for reading from said storage means and for writing from said storage means to said further memory,

said arithmetic means sequentially responsive to different range words and slope words in said further memory for algebraically adding said slope and range words, said arithmetic means simultaneously responsive to an associated span word for decrementing the same, and

control means for sequentially rewriting into said further memory said slope word, the range word and span word as modified by said arithmetic means unless said span word as decremented is less than a predetermined value.

9. The apparatus of claim 8 in which said further memory comprises three plural stage shift registers.

10. The apparatus of claim 8 in which said storage means stores in sequential locations, an azimuth word, and following said azimuth word parameters for indicia commencing at said azimuth and in which

said means for reading from said storage means includes a memory address counter clocked at a predetermined rate,

control means for enabling said memory address counter, said control means including a comparator with two inputs and an output, one said input provided with signals relating to antenna azimuth, a latch coupled to said other input for storing an azimuth word read from said storage means, said control means enabling said memory address counter when said comparator indicates antenna azimuth corresponds to said azimuth word.

11. The apparatus of claim 10 in which said control means further includes means for inhibiting said memory address counter unless said arithmetic means has decremented a span word to less than said predetermined value.

12. The apparatus of claim 11 in which said further memory comprises

a plurality of plural stage shift registers,

a multiplexer with plural input channels and an output coupled to said shift registers, one said input connected to receive data read from said storage means, a second said input connected to said shift registers, and a third said input connected to provide null data to said shift registers,

said control means controlling said multiplexer, to couple said first input to said output when data is read from said storage means, to couple said second input to said output when data is not being read and said arithmetic means has not decremented a span word to less than said predetermined value, and to couple said third input to said output when data is not being read and said arithmetic means has decremented a span word to less than said predetermined value.

13. A compressed data indicia generator for use with a display system to manifest visible fixed indicia concurrently and in coordination with visible manifestations of information bearing signals received by an antenna in which said display system includes a writing beam scanned over a display field by a deflection system in a predetermined pattern with a beam unblanking means for creating said manifestations, the indicia generator comprising:

a mixer for mixing information bearing signals with an output representing said indicia for controlling said beam unblanking means,

storage means storing data defining said indicia including at least coordinates of one point on said indicia and a slope and length of said indicia, and

first means coupled to said storage means and to said deflection system and providing indicia signals to said mixer for writing said indicia.

14. The apparatus of claim 13 in which said first means further includes, arithmetic means responsive to said stored data and coupled to said first means, for computing coordinates of said indicia other than said stored coordinates.

15. The apparatus of claim 14 which further includes:

a range clock for controlling said deflection system,

said first means comprising

means including plural scratch pad memories into which said arithmetic means writes information representing said coordinates, at least one said scratch pad memory coupled to said range clock at any time for reading out information stored therein to said mixer.

16. The apparatus of claim 15 in which

said plural scratch pad memories include three such memories, addressing means for each of said memories, means coupling said range clock to two said memories for reading out data from one of said two memories to said mixer, for nulling all locations of said other of said two memories as each location is addressed by said range clock,

and means coupling said arithmetic means to said third memory for writing new data therein as provided by said arithmetic means.

17. The apparatus of claim 14 in which said storage means stores an azimuth word followed by indicia parameters for indicia beginning at said azimuth and said first means includes

plural shift registers a different such register storing range words, slope words and span words,

loading means for loading said shift registers from said storage means, said loading means including

a multiplexer having an input connected to said storage means and an output connected to said shift registers,

addressing means for said storage means including a register for storing an azimuth word read from said storage means, an address counter clocked at a constant rate and control means for inhibiting said address counter if antenna azimuth does not correspond to said azimuth word in said register.

18. The apparatus of claim 17 in which said control means includes,

a comparator comparing antenna azimuth with said azimuth word in said register,

bistable circuit means coupled to said comparator and set to one position each time an azimuth word is loaded into said register and reset each time said comparator detects correspondence,

said control means inhibiting said addressing counter when said bistable circuit means is set.