Data communications system for a reproduction machine having a master and secondary controllers

• US 4,183,089 A
• Filed: 08/30/1977
• Issued: 01/08/1980
• Est. Priority Date: 08/30/1977
• Status: Expired due to Term

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Daughton, John W., Nelson, Frank M., Gillett, Kenneth
• Primary Examiner(s): Chapnick, Melvin B.
• Application Number:
  US05/829,013
• Time in Patent Office: 861 Days
• Field of Search: 364/900 MS File, 364/200 MS File, 364/104, 364/107, 355/14
• US Class Current: 710/21
• CPC Class Codes: G03G 21/14 Electronic sequencing control
• CPC Class Codes: G05B 19/0423 Input/output
• CPC Class Codes: G05B 2219/2214 Multicontrollers, multimicrocomputers, multiprocessing
• CPC Class Codes: G05B 2219/25178 Serial communication, data, also repeater
• CPC Class Codes: G05B 2219/25197 Optical, glass fiber

Abstract

A data communications system for an electrophotographic type reproduction machine or copier. The system includes a programmable master controller with memory and a command byte generator. A plurality of secondary controllers provide input data bytes reflecting the machine status to the master controller and receive command bytes from the master controller for operating the machine components. The secondary controllers are each connected to the master controller such that corresponding data bits of the secondary controller are ORed together to provide simultaneous transmission of input data bytes from the secondary controllers to the master controller while assuring that corresponding bits of the simultaneously transmitted bytes have mutually exclusive data therein.

Claims

1. For use in a reproducing machine having a plurality of devices for controlling said machine, a data communications system comprising:

a. a programmable master controller including;

1. master program memory storage means for storing program words defining an operating program,

2. addressing means for addressing said program words of said master program memory storage means,

3. an arithmetic and logic unit for processing said program words of said master program memory storage means, and

4. means for generating command bytes, said generating means operatively connected to said arithmetic and logic unit of said master controller, and

b. a plurality of additional controllers, each of said additional controllers including;

1. means for receiving command bytes from said master controller generating means, and

2. means for providing input data bytes indicative of the operation of at least some of said devices to said master controller arithmetic and logic unit,

c. said additional controllers having selected input data bits ORed together to provide at least one of said input data bytes, and

d. said additional controllers simultaneously transmitting said selected input bits comprising said one input data byte to said master controller arithmetic and logic unit in response to a predetermined command byte from said master controller generating means.

2. A data communications system as recited in claim 1, wherein said master controller further includes output data byte generating means, said output data byte generating means operatively connected to said arithmetic and logic unit of said master controller, and means for transmitting output data bytes from said output data byte generating means to said additional controllers for controlling said machine.

3. A data communications system as recited in claim 1 wherein said master controller further includes means for generating identifying addresses for said additional controllers and means for transmitting said identifying addresses to said additional controllers,

each of said additional controllers including decode logic means for decoding said addresses.

4. A data communications system as recited in claim 1 wherein at least one of said additional controllers is a programmable controller.

5. A data communications system as recited in claim 1 wherein said simultaneously transmitted data bytes provide an address for addressing a predetermined subroutine in said memory storage means.

6. A data communications system as recited in claim 1 including means for transmitting said input data bytes from said additional controllers in bit serial form to said master controller arithmetic and logic unit.