High density memory device

• US 4,183,095 A
• Filed: 09/01/1978
• Issued: 01/08/1980
• Est. Priority Date: 09/01/1978
• Status: Expired due to Term

• Current Assignee: NCR Corporation
• Original Assignee: NCR Corporation
• Inventors: Ward, William P.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US05/939,297
• Time in Patent Office: 494 Days
• Field of Search: 307/238, 365/49, 365/174, 365/189, 365/193, 365/200, 365/202, 365/206
• US Class Current: 365/189.02
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/414 for memory cells of the bipolar type
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A high density memory system is formed by reducing the number of electrical conductors that are needed to connect individual memory devices into an operable memory system. The reduction is accomplished by serially reading and writing data from and into selected memory elements on one function conductor while eliminating the need for additional control conductors by causing the state of the signal on a clock conductor as compared to the state of the signal on the function conductor at selected times to control the operating mode of the memory system.

Claims

1. A READ/WRITE memory system comprising:

a plurality of memory elements operatively connected in an addressable array;

a plurality of enabling means each operatively associated with a corresponding memory element for detecting the state of a clock signal and for enabling an associated memory element when the clock signal is of a first state and for disabling said associated memory element when the clock signal is of a second state;

means operatively connected to groups of said enabling means for applying a clock signal of a first state to said enabling means in response to an address selection signal and for applying to said enabling means a clock signal of a second state in the absence of an address selection signal;

a plurality of operating mode means each associated with a corresponding memory element for receiving a mode signal and for responding to said mode signal when said associated memory elements are enabled by placing said memory element in a READ mode in response to a mode signal of a first state and in a WRITE mode in response to a mode signal of a second state; and

means operatively connected to said operating mode means for controllably providing a mode signal of a first state to said plurality of memory elements to place enabled memory elements in a READ mode and for controllably providing a mode signal of a second state to place enabled memory elements in a WRITE mode.

2. A READ/WRITE memory system according to claim 1 wherein said means operatively connected to groups of said enabling means is comprised of:

a multiplexer having first and second inputs and an output, said first input adapted to receive a first state clock signal and said second input adapted to receive a second state clock signal, said multiplexer responsive to said address selection signal to gate said first state clock signal to said enabling means and responsive to the absence of said address selection signal to gate said second state clock signal to said enabling means.

3. A READ/WRITE memory system comprising:

a plurality of memory elements operatively connected in an addressable array;

a plurality of said addressable arrays;

decoder means for addressing selected ones of said addressable arrays;

a plurality of enabling means each operatively associated with a corresponding memory element for detecting the state of a clock signal and for enabling an associated memory element when the clock signal is of a first state and for disabling said associated memory element when the clock signal is of a second state;

clock means responsive to the addressing by said decoder means for applying a clock signal of a first state to said enabling means and for applying a clock signal of a second state in the absence of an addressing;

a plurality of operating mode means each associated with a corresponding memory element for receiving a mode signal and for responding to said mode signal when said associated memory elements are enabled by placing said memory element in a READ mode in response to a mode signal of a first state and in a WRITE mode in response to a mode signal of a second state; and

circuit means operatively connected to said operating mode means for controllably providing a mode signal of a first state to said plurality of memory elements to place enabled memory elements in a READ mode and for controllably providing a mode signal of a second state to place enabled memory elements in a WRITE mode.

4. The READ/WRITE memory system according to claim 3 wherein said decoder means is comprised of:

a comparator having one set of inputs corresponding to the assigned address of an associated addressable array and a second input for receiving the address of a to be addressed array, said comparator providing an enabling output when the address on said first and said second input are identical; and

a clock decoder having an enabling input operatively connected to receive the enabling output of said comparator, said clock decoder adpated to receive row select address signals and for enabling the clock means corresponding to the row select address.

5. The READ/WRITE memory system according to claim 3 and further comprising:

gating means interposed between said operating mode means and said circuit means for enabling said gating means in a first signal direction upon receipt of an address from said decoder means, and for enabling said gating means in a second direction in the absence of an address from said decoder means.

6. The READ/WRITE memory system according to claim 3 wherein said plurality of enabling means are pulse rate detectors for enabling a corresponding memory element when the clock signal is of a first rate and for disabling said memory element when the clock signal is of a second rate.

7. A READ/WRITE memory system comprising:

a plurality of memory elements operatively connected in groups to form addressable arrays;

a plurality of enabling means each operatively associated with a corresponding memory element for receiving a memory system synchronizing signal and for enabling an associated memory element upon detection of a change in the characteristics of said synchronizing signal;

decoder means responsive to a group address signal for providing a selection signal indicative of the particular group addressed;

synchronizing signal means responsive to said selection signal for providing a synchronizing signal to the group of said memory elements not selected and for providing a changed characteristic synchronizing signal to the group that is selected;

function driver and buffer circuit means operatively connected to groups of said memory elements for reading and writing data into a group of enabled memory elements in parallel; and

a plurality of operating mode means each associated with a corresponding memory element for receiving a mode signal from said function driver and buffer circuit and for responding to said mode signal when said associated memory elements are enabled by placing said memory element in a READ mode in response to a mode signal of a first state and in a WRITE mode in response to a mode signal of a second state.

8. A READ/WRITE memory system according to claim 7 wherein said synchronizing signal means is comprised of a plurality of multiplexers corresponding in number to the groups of said memory elements, each multiplexer having first and second inputs, and an output, said first input adapted to receive a synchronizing signal and said second input adapted to receive a synchronizing signal of changed character, said multiplexers responsive to said selection signal to gate the signal on said second input to said output and in the absence of said selection signal to gate the signal on said first input to said output, the outpt of each multiplexer being operatively connected to a corresponding group of memory elements.

9. The READ/WRITE memory system according to claim 7 wherein said plurality of enabling means are pulse rate detectors for enabling a corresponding memory element when the synchronizing signal is of a first rate and for disabling said memory element when the synchronizing signal is of a second rate.