High density floating gate electrically programmable ROM

• US 4,184,207 A
• Filed: 07/12/1978
• Issued: 01/15/1980
• Est. Priority Date: 01/27/1978
• Status: Expired due to Term

• Current Assignee: Palomar Technologies Incorporated
• Original Assignee: Texas Instruments, Inc.
• Inventors: McElroy, David J.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US05/923,876
• Time in Patent Office: 552 Days
• Field of Search: 357/23, 365/104, 365/182, 365/184, 365/185, 307/238, 307/279
• US Class Current: 365/185.16
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: H01L 21/033 comprising inorganic layers
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An N-channel double level poly, MOS read only memory or ROM array is electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by polycrystalline silicon row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate. A very dense array is obtained by a simplified manufacturing process which is generally compatible with standard N-channel silicon gate technology. Parallel strips of gate oxide, polycrystalline silicon, and nitride oxidation mask are applied, field oxide is grown, then a perpendicular pattern of strips is etched, removing field oxide as well as parts of the original strips, providing a diffusion mask. The second level poly is then applied as strips overlying the original strips.

Claims

1. An electrically programmable, nonvolatile, floating gate, semiconductor memory array comprising:

a plurality of MOS transistor devices each having a source, a drain, a floating gate, and a control gate, the floating gate being isolated from the channel between source and drain by thin oxide and the control gate being isolated from the floating gate by thin oxide, the transistor devices being arranged in an array of rows and columns, with the rows being separated by thick field oxide;

means connecting the control gates of all devices in each row together to provide row lines;

means including elongated parallel heavily-doped semiconductor regions forming the source and drain regions of the transistor devices connecting the sources and drains of all adjacent devices together to provide column lines;

the heavily-doped regions formed with the thick field oxide to provide a diffusion mask;

means for programming the array including means for selecting one of the row lines and applying a high voltage to it while applying a low voltage or reference potential to the remaining row lines, and means for selecting one pair of adjacent column lines and applying current through this pair while applying no current through all of the other pairs of column lines.

2. A memory array according to claim 1 wherein the transistor devices are N-channel and the floating gate and control gate are polycrystalline silicon.

3. A memory array according to claim 2 wherein means are provided for reading data from the array by applying an intermediate voltage to a selected one of the row lines, grounding one end of a selected one of the column lines, and applying a load device to the other end of the selected column line.

4. A memory array according to claim 1 wherein the sources, drains and channels of all transistor devices in each row are formed in one continuous elongated semiconductor region having heavily doped regions forming the sources and drains alternating with lightly doped regions forming the channels.

5. A memory array according to claim 4 wherein the row lines are elongated strips of polycrystalline silicon overlying the lightly doped regions.

6. An electrically programmable, nonvolatile, floating gate, semiconductor memory comprising:

an array of MOS transistors arranged in rows and columns, each transistor having a source, a drain, a floating gate, and a control gate;

each transistor having a thin insulating layer separating the floating gate and the control gate and a thin gate insulator separating the floating gate from a channel region between the source and drain;

means connecting the drain of each transistor in a row to the source of an adjacent transistor in the row so that each row is a source-to-drain series-connected plurality of transistors;

thick field oxide separating the rows from one another;

means including elongated heavily-doped semiconductor regions perpendicular to the rows connecting source and drains of adjacent transistors into column lines;

means for selectively applying high voltage to the control gates of a selected row while applying a low voltage or reference potential to other rows and applying current to a selected pair of adjacent columns to program the cell by charging the floating gate via electrons traversing the gate insulator.

7. A memory cell according to claim 6 wherein the rows are conductive material defining the control gates of a plurality of transistors.

8. A memory cell according to claim 7 wherein the MOS transistors are N-channel and the floating gates and control gates are polycrystalline silicon.

9. A memory cell according to claim 8 wherein the selected column has one end grounded and the other end connected through a load to a voltage supply.

10. A memory cell according to claim 9 wherein the intermediate voltage is at least threshold voltage and the high voltage is many times greater than threshold voltage.