Process and apparatus for the automatic inspection of patterns

• US 4,185,298 A
• Filed: 08/12/1976
• Issued: 01/22/1980
• Est. Priority Date: 08/13/1975
• Status: Expired due to Term

• Current Assignee: Compagnie Industrielle des Telecommunications Cit-Alcatel SA
• Original Assignee: Compagnie Industrielle des Telecommunications Cit-Alcatel SA
• Inventors: Billet, Gilles, Blottiau, Jean
• Primary Examiner(s): Griffin, Robert L.
• Assistant Examiner(s): Coles, Edward L.
• Application Number:
  US05/713,964
• Time in Patent Office: 1,258 Days
• Field of Search: 358/106, 358/107, 358/108, 358/212, 358/213, 356/163, 356/165, 356/166, 356/168, 356/169, 356/239, 356/240, 356/390, 356/237, 250/224, 250/560, 250/565, 235/92 QC, 235/92 CA
• US Class Current: 348/129
• CPC Class Codes: G01R 31/2806 Apparatus therefor, e.g. test stations, drivers, analysers, conveyors G01R31/2805, G01R31/281, G01R31/2818 take precedence
• CPC Class Codes: G01R 31/309 of printed or hybrid circuits or circuit substrates

Abstract

An object pattern to be inspected, such as a printed circuit board, and a reference pattern are scanned synchronously by respective cameras. The outputs of the cameras are compared and a fault signal is produced when the outputs do not coincide.

Claims

1. A process for the automatic inspection of patterns on printed circuits boards comprising positioning two cameras (3,4) each facing a corresponding printed circuit board (10,11), illuminating the printed circuits on said boards, one of the boards carrying a standard reference printed circuit, and the other a printed circuit to be inspected, providing said cameras with a strip of photodiodes lying in a plane parallel to said printed circuit boards, and effecting a comparison between said standard reference printed circuit and the printed circuit to be inspected by simultaneously:

a. scanning corresponding areas of the printed circuits of each board by synchronized relative translation of either the cameras or the boards, said relative translation and said scanning of the strips of photodiodes being co-ordinated to cause each board to be entirely explored,

b. effecting synchronized cyclic scanning of the photodiodes of said strips of photodiodes, and converting the analog signals delivered by the photodiodes into digital data and by comparing said digital data by a logic circuit providing a fault signal if comparison shows a difference between the boards, said analog signals derived from the cameras being converted into first digital data signals by comparison with a minimum voltage threshold, said first data signals corresponding to light being sensed by the photodiodes after passing through the boards or through holes in the boards, the absence of said first signals corresponding to the absence of light because of the printed circuit pattern, said analog signals which are produced by the sensed light passing through the holes being additionally converted into second digital data signals by comparison with a maximum voltage threshold.

2. A process according to claim 1 in which each of the said boards rests on a frame extending normal to the center-line of the scanning area of its respective camera so that the objectives of said cameras scan respectively, on each of said illuminated boards, a corresponding pattern area, said cameras being fixed and said frame being movable in two dimensions in its plane at a constant speed, said frame being laterally shifted at the end of a line of board scanning by a distance corresponding to the width of the area of the board sensed by the camera at any one instant.

3. A process according to claim 1 wherein the operation of producing the first and the second data signals of each camera is effected in first and second exclusive OR-circuits and data from the first and second exclusive-OR circuits is supplied to a third exclusive OR-circuit, so that the final resulting operation is a logic signal indicative of a difference or an identity between the pattern of a printed circuit area of the standard board and that of the corresponding area of the inspected board.

4. A process according to claim 3, in which the "fault" signal opens a pair of logic AND gates (CP1, CP2) the inputs of one of which are connected to a reader (LX) of the relative lateral positioning of the frame and the cameras and to a reader (LY) of the relative longitudinal positioning of said frame and the cameras, said circuits transmitting upon the "fault" signal the binary co-ordinates of the frame-camera to interface registers (R1,R2) of a registering unit (UE), said "fault" also being arranged to control a direct detection device to mark the pattern fault by depositing a small drop of ink in its immediate vicinity.

5. Apparatus for automatic inspection of patterns on printed circuit boards, said apparatus comprising a bench, a frame, means supporting said frame on said bench for displacement in the plane of the X and Y coordinates, said frame having two windows, a first board with a standard printed circuit thereon mounted on said frame at one of said windows, a second board with a printed circuit thereon to be inspected mounted on said frame at the other of said windows, two cameras equipped with a strip of photodiodes mounted on said bench, said cameras facing respective printed circuit boards for scanning corresponding areas of the printed circuits of each board, the displacement of said frame by the displacement means in the X-Y plane being coordinated with a cyclic scanning of the photodiodes of the strip to enable the cameras to scan synchronously the entire printed circuits on the boards, two light source means for illuminating said boards, and logic circuit means connected to said cameras for synchronously processing analog signals from the photodiodes thereof and for producing a logic signal when there is a fault in the printed circuit being inspected, said logic circuit means comprising means for converting the analog signals from the photodiodes of the cameras into first digital data signals by comparison with a minimum voltage threshold, said signals corresponding to light being sensed by the photodiodes after passing through the boards or through holes in the boards, the absence of said first signals corresponding to the absence of light because of the printed circuit pattern, means for converting those analog signals which are produced by passage of light through the holes into second digital data signals by comparison with a maximum voltage threshold, means for receiving the first and second digital data signals from each camera to produce a third digital data signal and means for comparing the third digital data signals from the two cameras to produce said logic signal indicative of a difference between said third signals signifying the presence of the fault in the printed circuit of the inspected board.

6. Apparatus according to claim 5 wherein the frame displacement means comprises a movable carriage shifted in the plane of the x, y co-ordinates, a slidable carriage (12) freely movable in a block (13), said block being longitudinally coupled to a worm-screw (14) driven by an electric motor (15) operated at a constant speed and inverted direction of rotation, said block being held during its travelling by a carrier-rod (19) laterally fixed to said block, said carrier-rod having free ends each supported by a bearing (20) free to slide along a guide-rod (16) having ends rigidly held in blocks (18), said block (13) being coupled to a worm-screw (21) extending parallel to said carrier-rod, a step-by-step electric motor 22 fixed to one end of said worm-screw and to said frame, and proximity indicator means for detecting the end of longitudinal travel of the frame in one direction or the other, so that, at the end of travel, the step-by-step electric motor produces lateral motion of said frame at a length equal to that of the scanning area of the camera.

7. Apparatus according to claim 5 in which each of the two light source means comprises three light sources, each board being disposed between the camera objective and the three light sources whose beams are directed to the area of the board normal to the center-line of the camera, two of said sources (S1, S2) being symmetrical to said center-line and the third source (S3) being of a weaker power and parallel with said center-line.

8. Apparatus according to claim 12 wherein each camera has an internal logic, one of said cameras imposing its clock pulse rate on the other by an electronic synchronization generating read enable signal (VAL) derived from a clock pulse by a counter corresponding to the number of photodiodes per strip of scanning area, said pulse being introduced in said cameras.

9. Apparatus according to claim 8 wherein said means for converting analog signals into second digital data signals comprises logic circuits having two voltage comparators (C2A, C2B) feeding respective analog signals from the cameras and converting them by comparison with the maximum voltage threshold into digital data signals (DEA,DEB) external to said cameras, said external digital signals being respectively presented at the first inputs E1 of a pair of bistable flip-flops (BA,BB) through a pair of NAND gates (PSA,PSB), said gates being active during each photodiode reading cycle, said clock pulse being connected in common to the input of said gates and to a second input (E2) of each flip-flop, so that external digital logic signals of said cameras are synchronized at the output of said flip-flops at the rhythm of said clock.

10. Apparatus according to claim 9 wherein the logic circuits are capable of producing a signal of a given logic status when there is a fault in the pattern, in which the outputs of a synchronization flip-flop of the external logic signals of each camera are each connected to said means which produces the third digital signal which comprises an "exclusive-OR" gate PA,PB, feeding internal signals DIA,DIB of the respective camera, the outputs of said gates being connected to the input of the means which produces said logic signal which comprises a third "exclusive OR" gate (PD) so that when the logic signals generated by the two first gates associated with the flip-flops are different, said third gate generates a given logic status signal showing a "pattern fault".