Signal bias remover apparatus
First Claim
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1. An equalizer input bias signal removal system for adjusting an analog input signal toward being symmetrical about a reference signal level where said analog input signal, combined with a correction signal, is to be converted by an analog-to-digital converter into a converter output signal in form of a digitized discrete time signal provided as a sequence of data samples each formed as a digital word comprising magnitude bits in a first sign bit, said bias signal removal system comprising:
- a transversal filter equalizer having an input and an output, said transversal filter equalizer being capable of receiving said converter output signal at an input thereof and being capable of providing an error sign bit signal at an output thereof, said error sign bit signal representing a sign of a difference between said transversal filter equalizer output and an allowed transmitted signal level;
a sign detection means having an input and an output, said sign detection means input being electrically connected to said transversal filter equalizer output to receive said error sign bit signal, said sign detection means providing a second sign bit signal comprising a sequence of second bits formed as one-bit digital words derived from said error sign bit signal at said sign detection means output;
a one-bit digital-to-analog converter means to receive said second sign bit signal and being capable of providing said correction signal in form of an analog signal having a polarity and amplitude depending on relative proportions of occurrence of said second sign bits in one of two logic states in a time duration recently passed; and
a first combining means capable of combining said correction signal with said analog input signal and of providing this combination to said converter.
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Abstract
An equalizer bias signal removal system for adjusting an analog input signal toward being symmetrical about a reference signal level where said analog input signal, combined with a correction signal, is to be converted by an analog-to-digital converter and provided to a transversal filter equalizer.
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Citations
1 Claim
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1. An equalizer input bias signal removal system for adjusting an analog input signal toward being symmetrical about a reference signal level where said analog input signal, combined with a correction signal, is to be converted by an analog-to-digital converter into a converter output signal in form of a digitized discrete time signal provided as a sequence of data samples each formed as a digital word comprising magnitude bits in a first sign bit, said bias signal removal system comprising:
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a transversal filter equalizer having an input and an output, said transversal filter equalizer being capable of receiving said converter output signal at an input thereof and being capable of providing an error sign bit signal at an output thereof, said error sign bit signal representing a sign of a difference between said transversal filter equalizer output and an allowed transmitted signal level; a sign detection means having an input and an output, said sign detection means input being electrically connected to said transversal filter equalizer output to receive said error sign bit signal, said sign detection means providing a second sign bit signal comprising a sequence of second bits formed as one-bit digital words derived from said error sign bit signal at said sign detection means output; a one-bit digital-to-analog converter means to receive said second sign bit signal and being capable of providing said correction signal in form of an analog signal having a polarity and amplitude depending on relative proportions of occurrence of said second sign bits in one of two logic states in a time duration recently passed; and a first combining means capable of combining said correction signal with said analog input signal and of providing this combination to said converter.
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Specification
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Current AssigneeHoneywell Incorporated (Honeywell International Inc.)
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Original AssigneeHoneywell Incorporated (Honeywell International Inc.)
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InventorsAcker, William F.
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Primary Examiner(s)Sloyan, Thomas J.
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Application NumberUS05/825,336Time in Patent Office895 DaysField of Search340/347 M, 340/347 CC, 340/348, 340/352, 325/38 B, 325/42, 179/15 AP, 332/11 DUS Class Current341/143CPC Class CodesH04L 25/03038 with a non-recursive struct...H04L 25/064 Subtraction of the threshol...
