Programmable communications subsystem

• US 4,188,665 A
• Filed: 11/29/1977
• Issued: 02/12/1980
• Est. Priority Date: 11/29/1977
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Petroskey, Paul W., van den Berg, Jan W., Wu, David C., Nagel, Dennis M., O'Neal, Douglas, Wildes, Donald V.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Heckler, Thomas M.
• Application Number:
  US05/855,572
• Time in Patent Office: 805 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 179/15 AL, 179/15 BV, 179/15 A
• US Class Current: 710/45
• CPC Class Codes: G06F 13/225 with priority control
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

A micro processor controlled user programmable communications multiplexer subsystem (herein referred to by the symbol PCS) capable of transmitting and receiving data on any one or more of 32 communications lines simultaneously. Each line may be dynamically assigned to a variety of communication characteristics, such as line speeds, character lengths, synchronous, or asynchronous operation, and code structures as well as protocol selections.

The system of the invention provides the capability for the user to write his communications programs using novel operations commands that provide code structure and protocol independence as well as communication line independence. Various hardware features and queuing techniques are employed in order to maintain high transmission rates.

Variable line scanning in the Teleprocessing Time Division Multiplexer of the PCS is programmably permissible; i.e., the time base for line scanning is fixed and is a multiple of the communication line rate, although the actual line to be scanned is programmably variable. The program ability is provided by a continuously scanned storage array which contains physical line addresses of the time division multiplexer. The scanning mechanism, while running, prioritizes the transmit buffer servicing of the individual lines.

Claims

1. In a communications multiplexer for transferring data between a central processor and a plurality of communications lines running to remote units, the combination comprising:

a scanner mechanism for selectively and repetitively transmitting data to and receiving data from different ones of the communications lines, each such communications line having a unique line address;

a storage mechanism having a separate data buffer for each communications line and a separate line control block for each communications line, each data buffer being located in its corresponding line control block;

a first-in-first-out transmit interrupt queue mechanism for receiving from the scanner mechanism the line addresses of those communications lines for which a processor-to-scanner data transfer operation is needed;

a line address register for receiving one line address at a time from the transmit queue mechanism and for supplying each such line address to the storage mechanism for addressing the corresponding line control block therein;

a controller mechanism responsive to an output of the transmit queue mechanism for performing during different time intervals the transfer of data between the central processor and any given data buffer and between the given data buffer and the scanner mechanism;

the controller mechanism including an interrupt mechanism responsive to the condition of the transmit queue mechanism when a valid line address appears at the output thereof for interrupting the controller mechanism and causing same to set such queue output line address into the line address register;

and the controller mechanism further including a first data transfer mechanism for transferring data from the central processor to the addressed line control block data buffer if such data buffer is empty and a second data transfer mechanism for transferring data from the addressed line control block data buffer to the scanner mechanism if such data buffer is not empty.

2. In a communications multiplexer for transferring data between a central processor and a plurality of communications lines running to remote units, the combination comprising:

a scanner mechanism for selectively and repetitively transmitting data to and receiving data from different ones of the communications lines, each such communications line having a unique line address;

a storage mechanism having a separate data buffer for each communications line and a separate line control block for each communications line, each data buffer being located in its corresponding line control block;

a first-in-first-out receive queue mechanism for receiving from the scanner mechanism the line address and a byte of received data each time the scanner mechanism has data ready for a particular communications line for transfer onward to the central processor;

a line address register for receiving one line address at a time from the receive queue mechanism and for supplying each such line address to the storage mechanism for addressing the corresponding line control block therein;

a controller mechanism responsive to an output of the receive queue mechanism for performing during different time intervals the transfer of data between the scanner mechanism and any given data buffer and between the given data buffer and the central processor;

the controller mechanism including a status sensing mechanism responsive to a valid line address at the output of the receive queue mechanism for causing the controller mechanism to set such line address into the line address register and to thereafter transfer the accompanying data byte to the data buffer in the line control block addressed by the line address register;

and the controller mechanism further including a second status sensing mechanism responsive to a full condition of a line control block data buffer for causing the controller mechanism to transfer the data in such data buffer to the central processor.

3. In a data processing system having a central processor, a main store, an I/O channel and means for cycle stealing data between the main store and the I/O channel, a programmable communications subsystem coupled to the I/O channel for controlling the transfer of data between the main store and a plurality of communication lines having different line addresses, said subsystem comprising:

a programmable controller;

storage means coupled to the programmable controller and having locations storing controller instructions for controlling the transfer of data and for storing line control blocks in a consecutive series of predetermined storage location groups, there being a separate line control block for each communications line with each line control block adapted to contain a current copy of status information, control information and at least one byte of data for its respective communications line;

address selection means including a storage address register means for accessing locations in said storage means other than said line control block locations;

means including said address selection means and a controller line address register for accessing said line control block locations;

program-controlled means coupled to the I/O channel and controlled by the programmable controller for initiating the cycle stealing of data bytes between the main store and the line block locations;

a receive data queue for storing data bytes received from the different communications lines in the order in which the data is received;

scanner means including a serializer-deserializer register for each communications line, a transmit buffer register for each communications line, means for controlling the transfer of data bytes between the lines and the serializer-deserializer registers in multiplexed fashion, and means for transferring each complete data byte, transferred from a communications line into the serializer-deserializer register, from the latter register into the receive data queue together with the line address of the communications line from which the byte is received;

program-controlled means including the controller line address register for reading each data byte and its line address from the receive data queue, for storing the line address in the controller line address register and for storing the data byte into the line control block corresponding to the line address in the controller line address register;

a scanner line address mechanism for accessing the different communications lines and their respective serializer-deserializer registers;

said scanner means including means effective each time a complete data byte is transferred from a serializer-deserializer register to a respective communications line for transferring a next-succeeding data byte from the corresponding transmit buffer register to the serializer-deserializer register;

a transmit interrupt queue;

said scanner means including means effective each time a data byte is transferred from a transmit buffer register to a serializer-deserializer register for transferring the line address being provided by the scanner line address mechanism to the transmit interrupt queue;

means including a hardware interrupt mechanism responsive to the entry of a line address into the transmit interrupt queue for initiating a hardware interrupt of the controller;

and program-controled means responsive to such hardware interrupts for reading the line addresses from the transmit interrupt queue and transferring data bytes from the corresponding storage means line control blocks to the corresponding transmit buffer registers.