Automatic zeroing system

• US 4,193,039 A
• Filed: 02/10/1978
• Issued: 03/11/1980
• Est. Priority Date: 02/10/1978
• Status: Expired due to Term

• Current Assignee: Gte Valeron Corp. (Verizon Communications Inc.)
• Original Assignee: Valeron Corp. (Sandvik AB)
• Inventors: Cook, Kenneth J., Massa, Richard L.
• Primary Examiner(s): Morrison, Malcolm A.
• Assistant Examiner(s): Chin, Gary
• Application Number:
  US05/876,918
• Time in Patent Office: 760 Days
• Field of Search: 364/571, 340/347 CC, 324/130, 328/162, 330/9
• US Class Current: 327/307
• CPC Class Codes: G01D 3/06 with provision for operation by a null method
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: H03M 1/1295 Clamping, i.e. adjusting the DC level of the input signal to a predetermined value

Abstract

An electronic apparatus for automatically zeroing or nulling an analog offset voltage by using multiple bit successive approximation to generate an analog zeroing voltage of equal magnitude and opposite polarity to that of the offset voltage, and then summing the zeroing voltage with the offset voltage.

Claims

1. Apparatus for automatically producing an analog zeroing voltage for nulling an offset voltage of either positive or negative polarity, said apparatus comprising:

polarity sensing means for sensing the polarity of a signal associated with the offset signal;

latch means coupled to the sensing means for providing a control signal whose state depends upon the polarity of the offset signal as determined by the sensing means;

voltage generator means for producing an output voltage of a magnitude substantially the same as the offset voltage;

inverter means for inverting the output voltage from the voltage generator;

switch means having two inputs, a control input and an output, one input being coupled to the unchanged output of the voltage generator means, with the other input being coupled to the output of the inverter means, and the control input being coupled to the output of said latch means, operative to couple one of its inputs to its output depending on the state of the control signal from the latch means whereby a zeroing voltage is provided of the same magnitude yet of opposite polarity to that of the offset voltage; and

summing means coupled to the output of said switch means for summing the zeroing voltage with the offset voltage.

2. Apparatus as defined in claim 1 wherein said voltage generator means further comprises:

means for making a plurality of changes in the magnitude of the analog zeroing signal, each change being a fraction of the previous change, and each change being selected to drive the sum of the analog zeroing signal and the analog offset signal toward zero from one direction.

3. Apparatus as defined in claim 2 wherein said voltage generator means further comprises:

cycle actuating means;

oscillating means; and

,

a multiple-bit successive approximation register connected to said cycle actuating means and said oscillating means.

4. Apparatus as defined in claim 3 wherein said cycle actuating means consists of a toggle switch or a remote contact closure.

5. Apparatus as defined in claim 3 wherein said oscillating means further comprises:

an electronic oscillator.

6. Apparatus as defined in claim 1 wherein said polarity sensing means comprises:

a comparator connected to an exclusive OR-gate.

7. Apparatus as defined in claim 1 wherein said latch means comprises:

an electronic flip-flop.

8. Apparatus as defined in claim 1 wherein said inverter means further comprises:

a unity gain inverter having an input and output, with said one input of said switch means being connected to the input of said inverter and the other input of said switch means connected to the output of said inverter.

9. Apparatus as defined in claim 1 wherein said summing means further comprises:

a unity gain summing amplifier.

10. Apparatus as defined in claim 9 wherein said summing amplifier further comprises:

an operational amplifier; and

three resistors each having one end connected to the input of said operational amplifier.

11. Apparatus as recited in claim 1 further comprising:

means coupled to said summing means for preventing indecision of a display device, operative to supply a predetermined voltage level to said summing means after generation of the zeroing signal.

12. Apparatus as defined in claim 11 wherein said means for preventing indecision of a display device further comprises:

a voltage source coupled to a resistive voltage dividing means; and

electronic analog switch means connecting said resistive voltage dividing means with said summing means, said electronic analog switch means having a control input coupled to said voltage generator means, operative to connect the output of the resistive voltage dividing means to said summing means after the generation of said zeroing voltage.

13. Apparatus as defined in claim 3 which further comprises:

means for indicating an overrange condition of said multiple-bit successive approximation register.

14. Apparatus as defined in claim 13 wherein said means for indicating an overrange condition further comprises:

a first NAND-gate having its inputs connected to some of a plurality of outputs of said multiple-bit successive approximation register;

a second NAND-gate having its inputs connected to the remaining outputs of said multiple-bit successive approximation register;

a NOR-gate having an output and two inputs, one input connected to the output of said first NAND-gate and the other input connected to the output of said second NAND-gate; and

a light emitting diode connected to the output of said NOR-gate.

15. Apparatus as defined in claim 3 which further comprises:

comparison means having two inputs and an output, one input being coupled to the output of said sensing means, the other input coupled to an output of the latch means, and the output coupled to a control input of the successive approximation register, operative to control the magnitude of the zeroing voltage generated by the register as a function of the comparison of the signals at its two inputs.

16. Apparatus as defined in claim 15 wherein said register includes a plurality of output lines, with said apparatus further comprising:

resistive means coupled to the output lines of the register, operative to provide sequentially decreasing output voltages depending on the state of the signals on the output lines from the register; and

said comparison means controlling the ultimate states of the signals on the output lines from the register wherein selected output voltages from the resistive means are utilized to form the final zeroing signal of a magnitude approximating the offset signal.