System for reception of frequency modulated digital communication signals

• US 4,197,501 A
• Filed: 06/28/1977
• Issued: 04/08/1980
• Est. Priority Date: 06/28/1976
• Status: Expired due to Term

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Kammerlander, Karl, Gammel, Josef, von der Neven, Hans-Juergen
• Primary Examiner(s): Bookbinder, Marc E.
• Application Number:
  US05/810,904
• Time in Patent Office: 1,015 Days
• Field of Search: 325/472, 325/474, 325/480, 325/315, 325/316, 325/302, 325/303, 325/304, 325/306, 325/320, 325/473, 178/88
• US Class Current: 375/334
• CPC Class Codes: H04L 27/14 Demodulator circuits; Receiver circuits

Abstract

A system for the reception of digital communication signals which are impressed in the form of a frequency modulation upon a carrier such that they are reflection free and can be used particularly for mobile stations, long distance traffic and scatter beam connections.

Claims

1. A system for the reception of FSK data signals, through a propagation medium that may have reflection paths and particular for reception at mobile stations of long-distance traffic and scatter beam traffic, wherein information losses caused by phase and amplitude distortions are automatically detected in two mutually supplementary arrangements one of which comprises a frequency discriminator (3) receiving the input data signals and a dynamic distortion corrector (DE) receiving the output of said discriminator (3) for recognizing and suppressing interference peaks caused by reflection distortions, said dynamic distortion corrector comprising a limit value device (4), a compensating circuit (6, 7) and a first output switch (5) controlled by the limit value device (4) and which substitutes said suppressed interference peaks at given signal amplitudes through switching the output of said dynamic distortion corrector from the output of said frequency discriminator (3) to the output of said compensating circuit (6, 7) which supplies to said first output switch (5) either the output of said FM discriminator (3) or the output of said compensating circuit (6, 7), and the other arrangement comprising a static distortion corrector (SE) which includes an AM demodulator (1), a polarization inverter (11) and a polarity integrator circuit (12), said polarity integrator circuit (12) receiving outputs from said AM demodulator (9) and said first output switch, said inverter receiving said AM demodulator output and an output from said polarity integrator (12) and produces a corrected signal indicative of the incoming FSK signals, a second output switch responsive to the output of said first output switch or the output of said polarization inverter, and an AM decision unit (14) responsive to the output of said AM demodulator to select one of the outputs of said first output switch or said polarization inverter for application to an output signal line.

2. A system for the reception of digital communication information as claimed in claim 1 including a common IF path, a limiter (2) supplying signals to the FM demodulator (3) and a dynamics compressor (8) supplying an input to the AM demodulator (9).

3. A system for the reception of digital communication information as claimed in claim 2 characterized in that said dynamics compressor (8) is designed as an amplifier having negatively logarithmic amplitude characteristics.

4. A system for the reception of digital communication information as claimed in claim 3, characterized in that said compensation circuit includes a delay line (6) which is connected to the output of said FM demodulator (3).

5. A system for the reception of digital communication information as claimed in claim 4 characterized in that an AM limiter (10) is connected between said AM demodulator (9) and said polarization inverter (11).

6. A system according to claim 1 characterized in that said dynamic distortion corrector consists of a double-voltage comparator (21) which has positive and negative thresholds which can be adjusted to reference levels and which receives the input signal, an OR gate (22) connected to the output of said comparator (21) a pulsing circuit (23) connected to said OR gate (22), a capacitor (C), a transit time delay line (20), a third switch (25) connected to said pulsing circuit (23) such that when the input signal exceeds said thresholds, switch (25) is closed briefly to transfer the instantaneous value of the input signal which has been delayed by a small time delay period by said transit time line (20) to said capacitor (C) and the charge of said capacitor (C) is maintained until said input signal falls below the threshold, a first change-over switch (30) connected to said capacitor (C) to provide an output (E), and circuit elements (23a, 24, 24a and 29) which, upon the closing of said switch (25), opens a short-circuit switch (27) in parallel with said capacitor (C), closes said first change-over switch (30), and opens a second change-over switch (32) which normally connects the delayed input signal to the output (E) for a period until the input signal no longer exceeds said threshold.

7. A system according to claim 6, characterized in that the output signal of said AM demodulator (9) is supplied to a clamping circuit (57) a low pass filter (56) receiving the output of said clamping circuit (57), an AM limiter (54) receiving the output of said low pass filter (56), the output signal of said AM limiter supplied to one input of said polarity inverter which comprises an exclusive OR gate (51), the output of said AM limiter being also supplied to a fourth switch (37) when the AM signal exceeds a certain level, said fourth switch (37) being closed thereby and connecting the FM signal to a second capacitor (C'"'"') and said second capacitor (C'"'"') produces a signal, a second low pass filter (42) connected to said second lowpass filter (42), a first pulse forming element (43) connected to the output of said second capacitor (C'"'"'), the output of said first pulse forming element (43) connected to the other input of said exclusive OR gate (51), a second pulse forming circuit (41, 40) receiving the output signal of said AM limiter (54), and from the leading ascending edges of this signal forming a pulse which is very short, a fifth switch (39) receiving said pulse from said pulse forming circuit (41, 40) to close it to discharge said second capacitor (C'"'"'), another switch (47) connected to the output signal of said exclusive OR gate (51), said another switch (47) being closed when there is a legible AM signal, and a data regenerator (48) connected to the output of said another switch (47).

8. A system according to claim 7, characterized in that a triggerable monostable flip-flop (44) is connected to the output of said first pulse forming element (43), a second logic gate (49) receiving the output of said monostable flip-flop (44), an AM decision circuit (52) receiving the AM signal at the output of said low pass filter (56), a triggerable monostable flip-flop (50) receiving the output of said AM decision circuit (52) and supplying its output to the other input of said second logic gate (49), and the output of said second logic gate (49) connected to said another switch (47) to close it, yet an additional switch (45) connected to receive the input FM signal and controlled by said second logic gate (49) in the case of legible FM signal data to be closed, and simultaneously open said another switch (47) to connect the FM signal to the input of the data-regenerator (48).