Semiconductor device

• US 4,197,555 A
• Filed: 07/18/1978
• Issued: 04/08/1980
• Est. Priority Date: 12/29/1975
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Tsuchimoto, Takamitsu, Uehara, Takao, Mukai, Makoto, Hamada, Katsuyuki, Masuzawa, Hideo
• Primary Examiner(s): Wojciechowicz, Edward J.
• Application Number:
  US05/925,788
• Time in Patent Office: 630 Days
• Field of Search: 357/40, 357/68, 357/70, 357/71
• US Class Current: 257/209
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An electronic device which includes at least one semiconductor chip with at least one circuit element thereon and connection patterns thereon being connected to the circuit element or elements. The connection patterns comprise a lower connection pattern, which is standardized and widely applicable to many kinds of circuits, and an upper connection pattern, which is positioned on the upper side of said lower connection pattern. The upper connection pattern and the lower connection pattern are connected in conformity with the desired circuit to be obtained.

Claims

1. A semiconductor device having a plurality of circuit elements formed therein, each of said plurality of circuit elements having more than one input terminal and each of said plurality of circuit elements having more than one output terminal, said semiconductor device having means for obtaining many kinds of desired circuits from the commonly formed device including a first connection layer having a standard pattern consisting of a plurality of redundant connection wires which are permanently connected to said output and input terminals of said plurality of circuit elements with said connection wires being arranged in parallel relationship to each other, a second connection layer which is arranged over the connection wire of said first connection layer and separated therefrom by an insulating layer, and consisting of a plurality of redundant connection wires arranged in parallel relationship to each other, and further arranged in a direction which intersects the parallel direction of the connection wires of said first connection layer, and means provided with said insulating layer between said first and second connection layers for providing interconnections therebetween, including via portions electrically connecting said first and second connection wires at cross points of said first and second connection wires.

2. A semiconductor device according to claim 1 wherein the connection wires of said second connection layer are used as standard connection wires regardless of whatever desired circuit is finally obtained;

and said via portions are only formed at predetermined ones of the cross points of the standard pattern redundant connection wires of said first and second connection layers for obtaining a desired circuit.

3. A semiconductor device according to claim 1, wherein the redundant connection wires of said second connection layer are used as standard connection wires regardless of the desired circuit finally obtained;

said via portions in said insulating layer being formed at all of the cross points of the connection strips of said first and said second connection layers;

and predetermined parts of said standard connection strips of said second connection layer being cut out for obtaining a desired circuit.

4. A semiconductor device according to claim 1, wherein said via portions of said insulating layer provides standard connection via portions which are respectfully connected to predetermined points of the standard wires of said first connection layer;

said connection via portions at said predetermined positions being selectively connected by the connection wires of said second said connection layer in accordance with a desired circuit to be obtained.

5. A semiconductor device according to claim 3, wherein said standard pattern redundant connection wires of said second connection layer is cut by means of a laser beam at predetermined portions.

6. A semiconductor device according to claim 3, wherein said standard pattern redundant connection wires of said second connection layer are cut by using a mask etching process at predetermined portions thereof.

7. A semiconductor device according to claim 1, wherein a plurality of the circuit elements are divided into a plurality of groups, each of the standard pattern of redundant connection wires of said first connection layer corresponding to the circuit elements of one group being connected to the standard pattern of redundant connection wires of said second connection layer corresponding to said circuit elements of another group.

8. A semiconductor according to claim 1, wherein each of said first and second connection layers, and said insulating layer therebetween having via portions for the interconnections are divided into a plurality of regions, each standard pattern of redundant connection wires of said first connection layer of each region being respectively connected to each standard pattern of redundant connection wires of said second connection layer of another adjacent region, and the connection wires of said second connection layer to said each region being connected to the standard connections wires of said first connection layer of another adjacent region.

9. A semiconductor device which includes at least one semiconductor chip forming circuit element thereon and connection patterns connected to said circuit element or elements, wherein said connection patterns comprise a lower connection pattern, which is standardized, which has a plurality of wire connection patterns arranged in parallel and which is commonly applied to many kinds of circuits, and an upper connection pattern which is standardized and positioned on the upper side of said lower connection pattern, and which has a plurality of wire patterns arranged in parallel and having a direction of about a right angle with respect to said lower connection pattern, and which is commonly applied to many kinds of circuits, vias which are standardized and arranged at all cross positions of said upper connection pattern and said connection patterns, and which are applied to many kinds of circuits, and wherein said upper connection pattern is formed by removing the lines of said upper connection pattern at positions which are not necessary for obtaining the desired circuit.

10. A semiconductor device which includes at least one semiconductor chip forming circuit element thereon and connection patterns connected to said circuit element or elements, wherein said connection pattern comprises a lower connection which is standardized, which has a plurality of wire connection patterns arranged in parallel and which is commonly applied to many kinds of circuits, vias which are positioned at standardized positions, and which are commonly applied to many kinds of circuits and an upper connection pattern which is formed in a special pattern for obtaining the desired circuit and which has a direction having about a right angle with respect to said lower connection pattern and vias which are necessary for obtaining the desired circuit are connected.

11. A semiconductor device which includes at least one semiconductor chip forming circuit element thereon and connection patterns connected to said circuit element or elements, wherein said connection patterns comprise a lower connection pattern, which is commonly standardized, which has a plurality of wire connection patterns arranged in parallel and which is applied to many kinds of circuits, and an upper connection pattern which is standardized and positioned on the upper side of said lower connection pattern, and which has a plurality of wire patterns arranged in parallel and having a direction of about a right angle with respect to said lower connection pattern, and which is commonly applied to many kinds of circuits, and said upper connection pattern and said lower connection pattern are connected at necessary positions for obtaining the desired circuit.