Signal holding circuit

• US 4,198,541 A
• Filed: 02/07/1978
• Issued: 04/15/1980
• Est. Priority Date: 02/08/1977
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Fukushima, Isao
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US05/875,797
• Time in Patent Office: 798 Days
• Field of Search: 179/1 P, 179/1 SW, 307/238, 307/239, 307/248, 307/251, 307/253, 325/348, 325/473, 325/475, 325/478, 325/480, 328/162, 328/165, 330/51
• US Class Current: 381/94.8
• CPC Class Codes: H03G 3/345 Muting during a short period of time when noise pulses are detected, i.e. blanking H03G3/348 takes precedence
• CPC Class Codes: H03K 17/16 Modifications for eliminating interference voltages or currents

Abstract

A signal holding circuit is disclosed in which a parallel circuit of a constant current source circuit comprising a transistor having a constant voltage supplied to a base thereof and a hold capacitor is connected to an emitter follower transistor, a first control transistor is connected between a base of the emitter follower transistor and ground, a second control transistor is connected between the base of the transistor of the constant current source circuit and ground, and a control pulse corresponding in time to a duration of the pulsive noise is applied to the bases of the first and second control transistors to render the first and second control transistors conductive only during the application of the control pulse so that a charging time constant of the hold capacitor during the conduction of the emitter follower transistor is reduced and a discharging time constant of the hold capacitor during the cutoff of the emitter follower capacitor is increased.

Claims

1. A signal holding circuit comprising:

an audio signal input terminal;

an audio signal output terminal;

an emitter follower transistor for introducing an audio signal supplied to said input terminal to said output terminal;

a constant current source transistor connected to an emitter of said emitter follower transistor for defining an emitter current thereof;

a control signal input terminal for receiving a control signal;

control circuit means connected between said control signal input terminal and the base of said emitter follower transistor and said constant current source transistor, and operative to substantially cut off said emitter follower transistor and substantially cut off said constant current source transistor when a control signal is applied to said control signal input terminal; and

a hold capacitor connected in parallel with said constant current source transistor, said audio signal being supplied to said hold capacitor when said emitter follower transistor is conducting, said hold capacitor functioning to hold an output level at the emitter of said emitter follower transistor to a level at a moment immediately before the cut off of said emitter follower transistor in accordance with the supplied audio signal when said emitter follower transistor is cut off.

2. A signal holding circuit according to claim 1, wherein said control circuit means includes a first control transistor which is rendered conductive by the control signal applied to said control signal input terminal to ground a base of said emitter follower transistor substantially cut off the emitter follower transistor, and a second control transistor which is rendered conductive by the control signal applied to said control signal input terminal to substantially cut off said constant current source transistor.

3. A signal holding circuit according to claim 1, wherein said constant current source circuit includes a constant current source transistor which is normally conductive and rendered nonconductive or substantially nonconductive when the control signal is applied to said control signal input terminal to float the emitter of said emitter follower transistor.

4. A signal holding circuit comprising:

an audio signal input terminal;

an audio signal output terminal;

an emitter follower transistor for introducing an audio signal supplied to said input terminal to said output terminal;

a constant current source transistor connected to an emitter of said emitter follower transistor for defining an emitter current thereof;

a control pulse input terminal for receiving a control pulse when a pulsive noise is superimposed on said audio signal, said control pulse corresponding in time to said pulsive noise and having a pulse width equal to or wider than a pulse width of said pulsive noise;

a first control transistor adapted to be forward biased into conduction by said control pulse supplied to said control pulse input terminal to ground a base of said emitter follower transistor to substantially cut off said emitter follower transistor,

a second control transistor adapted to be forward biased into conduction by the control pulse supplied to said control pulse input terminal to ground a base of said constant current source transistor to substantially cut off said constant current source transistor; and

a hold capacitor connected between the emitter of said emitter follower transistor and A.C.-wise ground, said audio signal being supplied to said hold capacitor when said emitter follower transistor is conductive, said hold capacitor functioning to hold an output level at the emitter of said emitter follower transistor to a level at a movement immediately before the cutoff of said emitter follower transistor in accordance with said audio signal supplied to said hold capacitor when said emitter follower transistor is cut off.

5. A signal holding circuit according to claim 4, wherein said emitter follower transistor and said constant current source transistor are composed of FET transistors.

6. A signal holding circuit comprising:

an audio signal input terminal;

an audio signal output terminal;

an emitter follower transistor for introducing an audio signal supplied to said input terminal to said output terminal;

a constant current source transistor connected to an emitter of said emitter follower transistor for defining an emitter current thereof;

a control D.C. signal input terminal for receiving a control D.C. signal;

a first control transistor adapted to be forward biased into conduction by the control D.C. signal supplied to said control D.C. signal input terminal to ground a base of said emitter follower transistor to substantially cut off said emitter follower transistor;

a second control transistor adapted to be forward biased into conduction by the control D.C. signal supplied to said control D.C. signal input terminal to ground a base of said constant current source transistor to substantially cut off said constant current source transistor; and

a hold capacitor connected between said emitter of said emitter follower transistor and A.C.-wise ground, said audio signal being supplied to said hold capacitor when said emitter follower transistor is conductive, said hold capacitor functioning to hold an output level at the emitter of said emitter follower transistor to a level at a moment immediately before the cut off of said emitter follower transistor in accordance with the audio signal supplied to said hold capacitor when said emitter follower transistor is cut off.

7. A signal holdingcircuit comprising:

a transistor of the type which includes a collecting electrode, an emitting electrode, and a control electrode and in which the conductivity between said collecting electrode and said emitting electrode is controlled by an input signal applied to said control electrode, and an output is produced from said emitting electrode;

biasing means connected to said control electrode of said transistor to apply a bias potential to said transistor to keep said transistor normally conductive;

a hold capacitor connected to said emitting electrode of said transistor;

impedance circuit means connected to constitute a parallel discharge circuit to said hold capacitor and normally assuming a low impedance; and

control circuit means responsive to the application of a control pulse which sustains for a predetermined period during which the input signal is to be blocked to change the bias potential applied to said transistor by said biasing means to a potential to substantially cut off said transistor and cause said impedance circuit means to assume a high impedance during the sustained period of said control pulse.

8. A signal holding circuit according to claim 7, wherein said impedance circuit means comprises a series circuit of a constant current source transistor which is biased to be normally conductive and a resistor, and said control circuit means comprises first and second control transistors adapted to receive said control pulse to conduct during the duration of said control pulse, said first control transistor being connected to said constant current source transistor such that when said, first control transistor conducts, it grounds the control electrode of said transistor, and said second control transistor being connected to said constant current source transistor such that when said second control transistor conducts, it cuts off said constant current source transistor.

9. A signal holding circuit according to claim 8, wherein said constant current source transistor comprises a bipolar transistor having a base biased to a potential sufficient to render said transistor conductive, and said second control transistor is connected to said constant current source transistor such that when said second control transistor conducts, it grounds the base of said constant current source transistor.

10. A signal holding circuit according to claim 7, wherein said impedance circuit means comprises a constant current source transistor having collector thereof connected to the emitting electrode of said transistor and a first current source connected to an emitter of said first constant current source transistor, and said control circuit means comprises a first control transistor having collector thereof connected to the control electrode of said transistor and base thereof adapted to receive said control pulse to render said first control transistor conductive during the duration of said control pulse, a second control transistor having base thereof adapted to receive said control pulse to render said second control transistor conductive during the duration of said control pulse and emitter thereof connected in common to the emitter of said constant current transistor, a third control transistor having emitter thereof connected in common to the emitter of said first control transistor, collector thereof connected to an operation voltage supply and base thereof connected in common to the base of said constant current source transistor, control biasing means for supplying a bias potential in common to the bases of said second and third control transistors to normally maintain said second and third control transistors conductive, and a second constant current source connected to the commonly connected emitters of said first and third control transistors, whereby said constant current source transistor and said third transistor conduct when said control pulse is absent and said second and third control transistors conduct when said control pulse is present.

11. A signal holding circuit according to claim 8, comprising means for generating a control pulse having a pulse duration of a noise pulse included in the input signal, wherein said first and second control transistors are adapted to receive said control pulse.

12. A signal holding circuit according to one of claims 7, 8, 9, 10, or 11, wherein said transistor is a bipolar transistor.

13. A signal holding circuit according to one of claims 7, 8, 9, 10, or 11, wherein said transistor is a field effect transistor.

14. A signal holding circuit comprising:

a transistor of the type which includes a collecting electrode, an emitting electrode, and a control electrode and in which the conductivity between said collecting electrode and said emitting electrode is controlled by an input signal applied to said control electrode, and an output is produced from said emitting electrode;

biasing means connected to the control electrode of said transistor to apply a bias potential to said transistor to keep said transistor normally conductive;

a hold capacitor connected between said emitting electrode of said transistor and A.C.-wise ground;

a constant current current source transistor connected to said emitting electrode of said transistor for defining an emitting electrode current thereof;

control circuit means responsive to the application of a control signal which sustains for a predetermined period during which the input signal is to be blocked to change the bias potential of said transistor to a potential to substantially cut off said transistor and cause said constant current transistor to substantially cut off during the sustained period of said control signal.

15. A signal holding circuit according to claim 14, wherein said control circuit means comprises:

a first control transistor adapted to be forward biased into conduction by the control signal to ground a base of said transistor to substantially cut off said transistor;

a second control transistor adapted to be forward biased into conduction by the control signal to ground a base of said constant current source transistor to substantially cut off said constant current source transistor;

said input signal being supplied to said hold capacitor when said transistor is conductive, said hold capacitor functioning to hold an output level at the emitting electrode of said transistor to a level at a moment immediately before the cut off of said transistor in accordance with the input signal supplied to said hold capacitor when said transistor is cut off.

16. A signal holding circuit comprising:

an emitter follower transistor of the type which includes a collector electrode, an emitter electrode, and a base electrode and in which the conductivity between said collector electrode and said emitter electrode is controlled by an input signal applied to said base electrode, and an output is produced from said emitter electrode;

a constant current source transistor connected to an emitter electrode of said emitter follower transistor for defining an emitter current thereof;

a control signal input terminal for receiving a control signal;

a first control transistor adapted to be forward biased into conduction by the control signal supplied to said control signal input terminal to ground a base of said emitter follower transistor to substantially cut off said emitter follower transistor;

second control transistor adapted to be forward biased into conduction by the control signal supplied to said control signal input terminal to ground a base electrode of said constant current source transistor to substantially cut off said constant current source transistor; and

a hold capacitor connected between said emitter electrode of said emitter follower transistor and A.C.-wise ground, said input signal being supplied to said hold capacitor when said emitter follower transistor is conductive, said hold capacitor functioning to hold an output level at the emitter electrode of said emitter follower transistor to a level at a moment immediately before the cut off of said emitter follower transistor in accordance with the input signal supplied to said hold capacitor when said emitter follower transistor is cut off.