CMOS Voltage multiplier

• US 4,199,806 A
• Filed: 01/18/1978
• Issued: 04/22/1980
• Est. Priority Date: 01/18/1978
• Status: Expired due to Term

• Current Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Patterson, Raymond B. III
• Primary Examiner(s): Shoop, William M.
• Application Number:
  US05/870,549
• Time in Patent Office: 825 Days
• Field of Search: 363/59, 363/60
• US Class Current: 363/60
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A CMOS voltage multiplier circuit comprised of one or more multiplier cells each of said cells including two P-channel devices functioning as switching elements to connect a cell contained capacitance in parallel across a voltage supply during one half of a cycle and a single N-channel device for connecting the capacitance in series with the supply during the other half of the cycle. An output stage is provided which includes a transfer device and a modified multiplier cell for driving the transfer device.

Claims

1. A voltage multiplier circuit for producing an output which is a multiple of a supply voltage supplied thereto, comprising a first CMOS multiplier cell, said CMOS cell being comprised of:

a pair of MOS devices of a first conductivity type;

a single MOS device of a second conductivity type;

and a capacitance means for storing voltage;

the source-drain conduction paths of said pair of MOS devices of the first conductivity type being serially connected with said capacitance means and said supply voltage such that said capacitance means lies between the source-drain conduction paths of said pair of MOS devices;

the source-drain conduction path of said single MOS device of the second conductivity type being connected between a first terminal of said capacitance means and said supply voltage, such that when the conduction paths of said pair of MOS devices of the first conductivity type are conductive, the capacitance means is connected in parallel with said supply voltage and when said conduction path of said single MOS device of the second conductivity type is conductive said capacitance means is serially connected to said supply voltage.

2. The voltage multiplier circuit of claim 1 further including a second CMOS multiplier cell of the same construction as said first CMOS multiplier cell, the source-drain conduction path of the single MOS device of the second conductivity type in said second multiplier cell being connected between a second terminal of the capacitance means of the first multiplier cell and a first terminal of the capacitance means of said second multiplier cell;

the pair of MOS devices of said first conductivity type in said second multiplier cell being serially connected with the capacitance means of said second cell and said supply voltage, such that conduction through the conduction paths of said pair of MOS devices causes said capacitance means to be charged from said supply voltage and conduction through said single MOS device causes the capacitance means of said first and second cells to be serially connected to said supply voltage.

3. The voltage multiplier circuit of claim 1 wherein said MOS devices of a first conductivity type are comprised of P-channel MOS devices and said MOS device of a second conductivity type is comprised of an N-channel MOS device.

4. The voltage multiplier circuit of claim 1 further including means for producing an input waveform cyclically varying between upper and lower voltage limits, an inverter means for inverting said input waveform, level shifter means responsive to the output from said inverter means for clamping said inverted input wave to a selected voltage level, the output from said level shifter being connected to said first CMOS multiplier cell to control the potential at the gate of the CMOS devices of said first multiplier cell, whereby the MOS devices of the first conductivity type and the MOS device of the second conductivity type are alternately rendered conductive through their respective conduction path in dependence upon the level of said input waveform.

5. The voltage multiplier circuit of claim 4 further including an output circuit comprised of an additional multiplier cell, a transfer device comprised of an MOS device of said first conductivity type and a holding capacitance means for accumulating the sum of the voltage supply and stored in said multiplier cells.

6. A CMOS voltage multiplier comprising:

a first CMOS multiplier cell including a pair of MOS devices of a first conductivity type, a capacitance means connected in series with the source-drain conduction path of said pair of MOS devices and a supply voltage, and a single MOS device of a second conductivity type having its source-drain conduction path connected between a first terminal of said capacitance means and said supply voltage;

output capacitance means having a first terminal connected to said voltage supply;

an output MOS device having its source-drain conduction path connected between a second terminal of the capacitance means of said first multiplier cell and a second terminal of said output capacitance means;

said capacitance means of said multiplier cell being connected in parallel with said supply voltage when the pair of MOS devices are conductive and said capacitance means of said multiplier cell and said output capacitance means being connected in series with each other and said supply voltage when the single MOS device and output MOS device are conductive.

7. The multiplier of claim 6 further including means for producing an input waveform cyclically varying between upper and lower voltage limits, an inverter means for inverting said input waveform, level shifter means responsive to the output from said inverter means for clamping said inverted input wave to a selected voltage level, the output from said level shifter being connected to said first CMOS multiplier cell to control the potential at the gate of the CMOS devices of said first multiplier cell, whereby the MOS devices of the first conductivity type and the MOS device of the second conductivity type are alternately rendered conductive through their respective conduction path in dependence upon the level of said input waveform.

8. The multiplier of claim 6 further including an output multiplier cell of the same construction as said first CMOS multiplier cell, the source-drain conduction path of the single MOS device of the second conductivity type in said second cell being connected between said second terminal of the capacitance means of the first multiplier cell and a first terminal of the capacitance means of said second multiplier cell;

the gate of said output MOS device being connected to a second terminal of said capacitance means of said second multiplier cell.

9. The multiplier of claim 6 wherein said pair of MOS devices are P-channel devices, said single MOS device is an N-channel device and said output MOS device is a P-channel device.