Method of integrating semiconductor components

• US 4,199,860 A
• Filed: 11/11/1977
• Issued: 04/29/1980
• Est. Priority Date: 11/11/1977
• Status: Expired due to Term

• Current Assignee: RCA Corporation (General Electric Company)
• Original Assignee: RCA Corporation (General Electric Company)
• Inventors: Preslar, Donald R., Beelitz, Howard R.
• Primary Examiner(s): Tupman, W. C.
• Application Number:
  US05/850,672
• Time in Patent Office: 900 Days
• Field of Search: 29/576 W, 29/577, 29/580, 357/15, 357/56
• US Class Current: 438/326
• CPC Class Codes: H01L 21/76245 using full isolation by porous oxide silicon, i.e. FIPOS techniques
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/76297 Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 27/0766 with Schottky diodes only
• CPC Class Codes: H01L 27/0826 Combination of vertical complementary transistors

Abstract

A dielectric-isolated PNP transistor with Schottky protection, either alone or as one of an integrated pair of complementary bipolar transistors has complete dielectric isolation from neighboring devices and from the substrate by means of a topside anisotropic etch. This leaves the devices in mesa form, thinner versions having the facility of lateral terminations, e.g. for the collector. The method is advantageously adapted to provide single type or complementary bipolars with integrated Schottky barrier protection.

Claims

1. A method of integrating semiconductor components comprising:

providing as starting bulk material a semiconductor single crystal body of low conductivity and having opposed major surfaces,

producing a collector region of the opposite conductivity at a first location in one of said surfaces and defining a collector region of said starting material at a second location in said one surface spaced from said first location,

insulatedly attaching a wafer handle to said one surface,

producing a base region, a base contact portion in the base region and an emitter region in the second major surface at each of said first and second spaced locations, the base contact portion at each location being produced simultaneously with the emitter region at the other location,

applying a Schottky barrier metallization to said starting material at one of said spaced locations on said second surface to form by virtue of the low conductivity of said material an integrated Schottky barrier,

applying associated terminal metallizations, and

anisotropically etching into said second surface as far as said one surface to form boundaries for surrounding said locations to thereby dielectrically isolate a complementary pair of semiconductor components in mesa form.

2. A method according to claim 1 comprising before attaching said handle, forming a low resistivity pocket on at least one collector region at said one surface whereby subsequently to provide a buried pocket.

3. A method according to claim 2 comprising forming a second low resistivity pocket located on a sloping side of a mesa formed by said etching, said second pocket contacting the first pocket.

4. A method of making a Schottky protected PNP bipolar transistor comprising:

providing a single-crystal semiconductor wafer as a bulk starting material of N-- conductivity and having opposed major surfaces,

forming a P- collector region over a limited area in one major surface of the wafer,

insulatedly attaching a wafer handle to said one surface to be used for the following steps;

forming an N- base portion in the N-- starting material in and at said opposite surface to lie superjacent the P- region, the unconverted N-- starting material completing an N type base region,

forming a P type emitter in said N- base portion,

applying a Schottky barrier forming metallization at said opposite surface to the residual N-- material completing said base region, and

anisotropically etching into said opposite surface as far as said one surface to provide an isolation moat and mesa formation for the PNP component, at any stage after the wafer handle attaching stage and to allow a surface communication with said P- region.

5. A method according to claim 4 comprising:

so forming the P- collector region that it does not reach said opposite surface of the wafer.

6. A method according to claim 5 comprising:

before attaching the wafer handle, forming a P+ collector contacting pocket at said one major surface, and subsequently

forming a further P+ contacting region at the lateral surface of said mesa extending down enough to contact said P+ pocket at the one major surface.

7. A method according to claim 6 comprising:

applying the Schottky metallization so that it bridges the N-- bulk to form the Schottky barrier and the further P+ contacting material at the lateral communication surface to form an ohmic contact thereat;

thereby also integrating a Schottky protection diode.

8. A method according to claim 4 comprising terminating the P- type collector region with separate metallization from that which forms the Schottky barrier with said N-- material.

9. A method according to claim 4 comprising:

also producing integral on the same wafer but dielectrically isolated an NPN transistor with a common electrode forming a Schottky barrier with said N-- wafer bulk material,

said common electrode also ohmically contacting the P type base of said NPN transistor.