Weighted capacitor analog/digital converting apparatus and method

• US 4,200,863 A
• Filed: 12/11/1978
• Issued: 04/29/1980
• Est. Priority Date: 10/03/1977
• Status: Expired due to Term

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Gray, Paul R., Hodges, David A., McCreary, James L.
• Primary Examiner(s): Miller, Charles D.
• Application Number:
  US05/968,590
• Time in Patent Office: 505 Days
• Field of Search: 340/347 AD, 340/347 DA, 340/347 M, 340/347 C
• US Class Current: 341/156
• CPC Class Codes: H03M 1/203 using an analogue interpolation circuit
• CPC Class Codes: H03M 1/38 sequentially only, e.g. successive approximation type converting more than one bit per step H03M1/14

Abstract

An array of binary weighted capacitors, an additional capacitor having a capacitance value equivalent to that of the least of the binary weighted capacitors, a voltage comparator, switches for interconnecting the capacitors with certain predetermined voltage levels and the comparator, and a sequencing circuit are included. One side of all of the capacitors is connected to one input terminal on the comparator and the other side has applied thereto the signal to be quantized. Switch sequencing combines divided portions of a reference voltage with the signal to be quantized for presentation to the input of the comparator which thereby provides a serial digit output connected to the sequencing circuit. In this fashion, a linear conversion between an analog and a digital signal is made by the sequencing circuit. A nonlinear converter between digital and analog signal presentation is also disclosed. Resolution of the coder/decoder is increased by providing a reference voltage generator capable of supplying stepped increments of the reference voltage to the capacitor array during the comparison process.

Claims

1. In an analog/digital converter for converting between an analog and a digital signal, said converter comprising an array of binary weighted capacitors having capacitance values corresponding to a predetermined number of binary bits ranging from a most to a least significant bit, a common plate node within said array, a voltage comparator having first and second input terminals and an output terminal, said common plate node being connected to said first input terminal, said second input terminal being connected to a first predetermined reference, a digital control circuit coupled to said output terminal, a first switch operated by said digital control circuit to selectively connect said common plate node to said first predetermined reference, a second switch operated by said digital control to alternately select the analog signal and a second predetermined reference, and a first plurality of additional switches operated by said digital control circuit, each of said first plurality of additional switches being configured to selectively connect ones of said array of binary weighted capacitors to said first predetermined reference and said second switch, said digital control circuit being responsive to a serial digit input sequence so that said array of binary weighted capacitors sequentially samples and holds the analog signal, divides said second predetermined reference signal into binary weighted portions, combines the binary weighted portions with the analog signal to provide combined signal levels, and said comparator compares each of said combined signal levels with said first predetermined reference, whereby said voltage comparator quantizes said analog signal as a serial digit output at said output terminal, the improvement comprising means for dividing said second predetermined reference into a plurality of incremental sub-intervals, and means for determining the individual one of said incremental sub-intervals within which said analog signal lies.

2. The combination of claim 1 wherein said dividing means comprises a resistor string network having a plurality of taps.

3. The combination of claim 2 wherein said determining means includes a second plurality of additional switches coupled to different ones of said taps and said digital control circuit.

4. An analog/digital converter as in claim 1 wherein said array of binary weighted capacitors, additional capacitor voltage comparator, digital control circuit, first and second switches, plurality of additional switches, dividing means and determining means are on a single semiconductor chip.

5. In a method of converting between an analog and a digital indication comprising the steps of (a) weighting an array of capacitors to assume capacitance values in digital relation from a most to a least significant digit, (b) connecting one side of each capacitor in the array to a common point, discharging the array of capacitors, (c) sampling an analog signal by charging the uncommon sides in the array of capacitors with the analog signal, (d) holding the sampled charge on the array of capacitors by coupling the uncommon sides to a first charge reference level, (e) connecting a second reference charge level from a reference energy source to the uncommon side of each capacitor in the array in predetermined sequence, thereby redistributing charge therebetween and producing a predetermined sequence of trial signals on the common point, (f) coupling the common point to a comparator input, (g) coupling another input on the comparator to the first charge reference level so that a serial digit output is provided at the output of the comparator in accordance with serial comparisons between the second reference and trial signals, said step (e) of connecting a second reference charge level in predetermined sequence operating to cause the trial signals to converge toward the first charge reference level, whereby charge on parasitic capacitance in the converter appearing between the common point and the second reference charge level converges toward the charge level attained during the step of holding, and (h) sequencing the steps of discharging, sampling, holding and redistributing so that the serial digital output is in a predetermined digit sequence, the improvement wherein said step (e) of connecting includes the steps of providing a plurality of incrementally spaced second reference charge levels, and determining that one of said spaced charge levels to which said sampled analog charge most closely compares.