Buffered high frequency plasma display system

• US 4,200,868 A
• Filed: 04/03/1978
• Issued: 04/29/1980
• Est. Priority Date: 04/03/1978
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Martin, William J., Lamoureux, William R., Trushell, James B.
• Primary Examiner(s): Curtis, Marshall M.
• Application Number:
  US05/892,703
• Time in Patent Office: 757 Days
• Field of Search: 340/758, 340/771, 340/774, 340/776, 340/777, 340/779, 340/789, 340/791, 340/805, 340/811, 340/166 EL, 340/168 S, 340/713
• US Class Current: 345/60
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 3/291 controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
• CPC Class Codes: G09G 3/296 Driving circuits for producing the waveforms applied to the driving electrodes

Abstract

A plasma discharge display device is operated at a high frequency above the response range of the inherent wall charge storage phenomenon and utilizes a refresh buffer. The vertical drive selection includes a pair of shift registers operated in parallel into which data from the host or associated controller is loaded, with an individual driver associated with each register stage. The horizontal lines are addressed through associated shift registers in an even-odd interlace sequence to generate a display on a horizontal scan basis. The horizontal drivers are referenced at the level and frequency of the high frequency energizing signals, while the vertical drivers are selectively set to ground or a positive a.c. voltage according to the state of associated register cells. By using the high frequency signal in the horizontal axis as a floating reference and unique selection techniques, the display is operated by low voltage signals. The normal sustain and erase operations associated with conventional plasma discharge devices are eliminated, while the write operation does not require either the precise timing or logical considerations associated with the selective operation of conventional plasma discharge display devices. The low voltage drive requirements permits use of low voltage driver circuitry which is susceptible to low cost monolithic fabrication techniques.

Claims

1. A refresh buffer plasma display system comprising in combination,

a plasma display device comprising first and second glass plates,

said plates being sealed under pressure and containing an ionizable gas,

said first and second plates having first and second dielectric coated arrays of parallel conductors respectively formed thereon,

said first and second conductor arrays being orthogonally disposed with respect to each other whereby the intersections of said orthogonal conductors define a matrix of gaseous discharge cells,

a high frequency signal source having a repetition rate above the wall charge response time of said gaseous discharge cells to prevent the accumulation of wall charge on said cells during operation of said device,

first and second drive-selection circuits associated with said first and second conductor arrays,

means responsive to control signals applied to said first drive-selection circuits for selectively conditioning conductors on one of said arrays in response to data signals applied thereto, and

means responsive to control signals applied to said second drive-selection circuits for selectively and sequentially scanning a plurality of conductors in said second array with said high frequency signal source and applying drive signals referenced to said high frequency signal source to selected lines whereby selected cells in said array are ionized by coincidence of said conditioning and said scanning signals.

2. A system of the type claimed in claim 1 wherein said high frequency signal is applied to all conductors on one of said arrays.

3. A system of the type claimed in claim 1 wherein said first and second selection circuits comprise vertical and horizontal selection circuits respectively.

4. A system of the type claimed in claim 1 wherein said conditioning means is applied to said vertical axis and said scanning means is applied to said horizontal axis.

5. A system of the type claimed in claim 3 wherein said vertical selection circuits comprise interleaved shift registers connected to conductors alternately terminated on opposite sides of the panel.

6. A system of the type claimed in claim 3 wherein said horizontal selection circuits comprise serially connected interlaced shift registers operated as a ring counter for providing an interlaced display.

7. A system of the type claimed in claim 5 wherein said vertical shift registers are loaded and operated in parallel to reduce data load time.

8. A device of the type claimed in claim 3 wherein said first drive-selection circuits apply a pulse signal to selected vertical lines while a similar signal referenced to said high frequency signal is applied to said horizontal conductors whereby a horizontal slice of data is simultaneously generated for display.

9. A device of the character claimed in claim 8 wherein said horizontal and vertical drive-selection circuits include shift register means for entering and shifting data to control the operation of drivers associated with each row and column in said matrix display.