Clock pulse signal generator having an automatic frequency control circuit
First Claim
1. A clock pulse generator comprising:
- input means for receiving an external reference signal;
controlled oscillator means for generating a clock signal whose frequency is varied by a control signal applied to said oscillator means;
counter means for frequency-dividing said clock signal to obtain a comparing signal having substantially the same frequency as said external reference signal;
phase comparator means for comparing the phase of said comparing signal with the phase of said external reference signal and providing said control signal in correspondence to a detected phase difference therebetween;
first signal forming means for forming a window pulse between a first count and a second count of said counter means;
second signal forming means for generating a further pulse having a pulse width narrower than the width of said window pulse and in a predetermined time relation with said external reference signal;
detecting circuit means for providing a first detecting signal whenever said further pulse occurs substantially during said window pulse, and a second detecting signal whenever said further pulse occurs substantially at a time other than during said window pulse; and
means responsive to said first and second detecting signals for selectively inhibiting said control signal when said further pulse does not occur substantially during said window pulse, including means for generating a hold signal in response to a succession of a predetermined number of said first detecting signals; and
, means for causing said counter means to hold the count stored therein in response to said hold signal.
0 Assignments
0 Petitions
Accused Products
Abstract
A clock pulse generator which has the frequency of its output automatically controlled by comparison of the generated clock pulses with an external reference signal comprises an input for receiving the reference signal, a voltage controlled oscillator for generating the clock pulses, a counter for frequency-dividing the clock pulses to obtain a comparing signal having substantially the same frequency as the external reference signal, a phase comparator for comparing the phase of the comparing signal with the phase of the external reference signal and providing the control voltage for the oscillator in response to a detected phase difference therebetween, and an inhibiting circuit for inhibiting the control voltage whenever the phase of the external reference signal is outside a predetermined range with respect to the comparing signal.
37 Citations
4 Claims
-
1. A clock pulse generator comprising:
-
input means for receiving an external reference signal; controlled oscillator means for generating a clock signal whose frequency is varied by a control signal applied to said oscillator means; counter means for frequency-dividing said clock signal to obtain a comparing signal having substantially the same frequency as said external reference signal; phase comparator means for comparing the phase of said comparing signal with the phase of said external reference signal and providing said control signal in correspondence to a detected phase difference therebetween; first signal forming means for forming a window pulse between a first count and a second count of said counter means; second signal forming means for generating a further pulse having a pulse width narrower than the width of said window pulse and in a predetermined time relation with said external reference signal; detecting circuit means for providing a first detecting signal whenever said further pulse occurs substantially during said window pulse, and a second detecting signal whenever said further pulse occurs substantially at a time other than during said window pulse; and means responsive to said first and second detecting signals for selectively inhibiting said control signal when said further pulse does not occur substantially during said window pulse, including means for generating a hold signal in response to a succession of a predetermined number of said first detecting signals; and
, means for causing said counter means to hold the count stored therein in response to said hold signal. - View Dependent Claims (2, 3, 4)
-
Specification