Pseudostatic electronic memory

• US 4,203,159 A
• Filed: 10/05/1978
• Issued: 05/13/1980
• Est. Priority Date: 10/05/1978
• Status: Expired due to Term

• Current Assignee: Frank M. Wanlass
• Original Assignee: Frank M. Wanlass
• Inventors: Wanlass, Frank M.
• Primary Examiner(s): Hecker, Stuart N.
• Application Number:
  US05/948,683
• Time in Patent Office: 586 Days
• Field of Search: 365/222, 365/149, 365/150
• US Class Current: 365/222
• CPC Class Codes: G11C 11/402 with charge regeneration individual to each memory cell, i.e. internal refresh
• CPC Class Codes: G11C 11/4023 using field effect transistors

Abstract

An electronic memory is described which has only two transistors in each memory cell, but does not require that data processing be periodically interrupted to enable refreshing. It adds to a typical, single transistor cell dynamic memory one additional transistor per cell, and a duplication of the driving and sensing circuitry typically included in such a memory. The additional transistor in each cell provides access to the same for refreshing, which refreshing is accomplished by the additional driving and sensing circuitry at the very same time the memory is otherwise being accessed for data processing.

Claims

1. A pseudostatic electronic memory comprising:

A. an array of capacitative memory cells, each one of which is adapted to hold any one of a plurality of different amounts of electrical charge representative of information to be stored and includes;

(1) a first electronic switch for controlling the application and sensing of charge on said cell;

(2) a single second electronic switch for controlling periodic detection and refreshing of the charge on said cell;

B. means both to apply electrical charge to said cells and to sense the amount of charge thereon at any given time;

C. means independent of said charge application and sensing means to detect and refresh periodically the amount of charge on each of said cells;

D. the operation of said first electronic switch being controlled by the voltage state present on a word line of said array, and the charge on said cell being sensed and applied thereto through a bit line of said array; and

E. the operation of said second electronic switch being controlled by the voltage state present on a second word line of said array, and the charge on said cell being detected and refreshed periodically through a second bit line of said array.

3. A pseudostatic electronic memory according to claim 1 wherein each of said switches is a field effect transistor.

4. A pseudostatic electronic memory according to claim 3 wherein each of said cells further includes a capacitor for storing said electrical charge representative of information to be stored.

5. A pseudostatic electronic memory according to claim 1 wherein means are included to prevent erroneous determinations of the information represented by said cell from being caused by the operation of refreshing said charge through said second switch.

2. A pseudostatic electronic memory according to claim 2 wherein in each of said cells there is only one first electronic switch for controlling the application and sensing of charge on said cell.