Method of determining the open circuit voltage of a battery in a closed circuit

• US 4,204,153 A
• Filed: 09/01/1978
• Issued: 05/20/1980
• Est. Priority Date: 09/01/1978
• Status: Expired due to Term

• Current Assignee: The Dow Chemical Company (Dow, Inc.)
• Original Assignee: The Dow Chemical Company (Dow, Inc.)
• Inventors: Brown, William E.
• Primary Examiner(s): Tokar, M.
• Application Number:
  US05/939,157
• Time in Patent Office: 627 Days
• Field of Search: 320/48, 324/29.5
• US Class Current: 324/429
• CPC Class Codes: G01R 19/16542 for batteries charge condition monitoring in G01R31/36
• CPC Class Codes: G01R 31/389 Measuring internal impedance, internal conductance or related variables

Abstract

The open circuit voltage of a battery which is connected in a closed circuit is determined without breaking the circuit or causing voltage upsets therein. The closed circuit voltage across the battery and the current flowing through it are determined under normal load and then a fractional change is made in the load and the new current and voltage values determined. The open circuit voltage is then calculated, according to known principles, from the two sets of values.

Claims

1. A method of determining the open circuit voltage of a battery or cell operating in a closed circuit, without interrupting said circuit or substantially destabilizing said battery or cell, said method comprising:

(1) measuring the battery or cell current (I₁) and voltage (E₁) under a given load,

(2) altering said load by a fractional amount and remeasuring the battery or cell current (I₂) and voltage (E₂) under the altered load, and

(3) calculating the open circuit voltage (E_oc) of the battery or cell from the relationship

space="preserve" listing-type="equation">E.sub.oc =E.sub.1 +(Δ

E/Δ

I)I.sub.1,

where Δ

E is the absolute difference between E₁ and E₂ and Δ

I is the absolute difference between I₁ and I₂, the algebraic sign of I₁ being negative when the battery or cell is on charge and positive on discharge.

2. The method of claim 1 in which said load alteration is effected by connecting a resistor in parallel with a known in-line resistance in said circuit, the resistance ratio being such that the overall resistance of the circuit will not thereby be decreased by more than about 25%.

3. The method of claim 2 in which said ratio is at least 9:

1.