Input-output unit for a microprocessor engine control system

• US 4,204,256 A
• Filed: 06/19/1978
• Issued: 05/20/1980
• Est. Priority Date: 07/20/1977
• Status: Expired

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Klotzner, Winfried
• Primary Examiner(s): Gruber, Felix D.
• Application Number:
  US05/916,827
• Time in Patent Office: 701 Days
• Field of Search: 364/424, 364/431, 364/442, 364/900, 364/200, 123/32 EC, 123/117 D, 123/119
• US Class Current: 701/115
• CPC Class Codes: F02B 1/04 with fuel-air mixture admission into cylinder
• CPC Class Codes: F02P 3/0558 using digital techniques
• CPC Class Codes: F02P 5/1502 using one central computing unit
• CPC Class Codes: Y02T 10/40 Engine management systems

Abstract

Repetitive operations, such as fuel injection and/or ignition timing of a gasoline engine, are controlled by a microprocessor with reference to engine operation parameters that provide electrical inputs in a manner achieving increased efficiency and economy by the provision of an input-output unit that supplies considerable preprocessing of the input signals under control of the microprocessor through the usual data and address buses. Counters are operated to count down from count limit values. The counting rate, as well as the count limit values, are capable of being varied by commands through the data bus, from time to time, so as to make the capabilities of the system adaptable to a wide variety of particular engines. The system is readily programmable for a particular application or machine if a programmable read-only memory (PROM or EPROM) is used for programming the microprocessor.

Claims

1. In a system for controlling repetitive operations of a machine dependent on operating parameters such as the operation of electrical ignition in an internal combustion engine, which system comprises a microprocessor, a clock pulse generator, a read-only memory (ROM, PROM), a random access memory (RAM), a data bus and an address bus, both interconnecting said microprocessor with said read-only memory and said random access memory, and read and write enable connections for enabling the reading of said memories and writing into said random access memory the data on said data bus at the memory address specified on the said address bus,

an input-output unit for said system connected to said address bus and read and write connections including a decoding circuit, connected to said data bus, and connected to said microprocessor also through "clear" and "interrupt" connections for receiving a clearing command from said microprocessor and for providing an interrupt to said microprocessor, said input-output unit comprising:

a counter (61) for counting shaft rotation rate dependent signals arranged for operation in successive counting invervals, the length of which intervals are determined by setting of said counter through said data bus (14), and the position in time of which intervals is controlled by at least one timing reference mark of said machine, said counter having a multibit count state output and having input connections for having a count value set therein for initiation of counting and termination of and for counting said signals;

a comparator (64) and a buffer store (68) therefor, said comparator having one multibit comparison input connected to the count-state output of said counter (61) and its other multibit comparison input connected to said buffer store (68), and having an output for indicating at least one comparison condition of signals at said inputs thereof, said buffer being arranged to have its content written through said data bus;

a selectable multi-channel final stage array (75, 76, 49,

     50) and providing a plurality of output command channels,

and select logic circuits (72,

     73) for sequential preselection of said channels of said final stage array, said select logic circuits being connected to said data bus for their control and to said final stage array for channel preselection in response to a signal of a control signal sequence (F) and including circuits for transferring timed signals (E) obtained in response to the output of said comparator to the channels preselected in sequence,

said decoding circuit (100) being constituted so as to provide stepwise control of the various circuit components connected with said data bus (14) as selected over said address bus (15).

2. An input-output unit for an operation control system containing a microprocessor, as defined in claim 1, wherein an OR-gate (67) is provided having one input responsive to a signal resulting from said timing reference mark, and another input responsive to the overflow output of said counter (61) for generation of additional timing reference signals for controlling the position in time of said intervals.

3. An input-output unit for an operation control system containing a microprocessor, as defined in claim 1, wherein a frequency multiplying stage (60) is interposed in the input connection of said counter (61) for counting said signals.

4. An input-output unit for an operation control system containing a microprocessor, as defined in claim 1, wherein a second counter (112) is provided which is arranged for being supplied with at least one magnitude value of an operating parameter of said machine in the form of a frequency and which is arranged to have its counting time prescribed by a timing circuit (85, 88), and furthermore, is arranged so that its count result is transferable through a gate stage (113) to said data bus (14).

5. An input-output unit for an operation control system containing a microprocessor, as defined in claim 4, wherein means are provided for supplying a plurality of magnitude values dependent upon operating parameter values of said machine through a transfer switching device (110) to said second counter (112) and means are also provided for control of said transfer switching device (110) through a parameter selection decoder stage (118) controlled by said data bus (14), said decoder stage having an enabling input controlled by an output (74) of said decoding circuit (100).

6. An input-output unit for an operation control system containing a microprocessor, as defined in claim 4, wherein said timing circuit (85,88) comprises a third counter for counting at a predetermined counting frequency and arranged for being supplied a count content from said data bus (14) in response to an enabling signal from an output (87) of said decoding circuit (100) for use of said count content as a number from which down counting is performed by said counter.

7. An input-output unit for an operation control system containing a microprocessor, as defined in claim 6, wherein a frequency selection decoder stage (119) and a frequency selecting circuit (117) controlled through said frequency selection decoder stage in response to an output (74) of said decoding circuit (100), whereby said predetermined counting frequency is subject to being varied over said data bus.

8. An input-output unit for an operation control system containing a microprocessor, as defined in claim 6, wherein a stage (79) for evaluation of shaft speed with respect to a speed threshold value is provided for cutting off the quiescent current of said final stage array (49, 50) by providing a signal for transfer into said data bus (14) in response to recognition that said shaft rotation speed is less than said speed threshold value.

9. An input-output unit for an operation control system containing a microprocessor, as defined in claim 8, wherein said shaft speed evaluation stage (79) is constituted in the form of a counting frequency counter that operates in successive counting intervals, the beginning of each of which intervals is determined by shaft rotation speed signals and that are arranged to provide a signal representative of the reaching of a shaft rotation speed lower threshold when the count content reaches a predetermined value.

10. An input-output unit for an operation control system containing a microprocessor, as defined in claim 9, wherein means are provided for varying said shaft rotation speed lower threshold by variably setting the counter of said shaft rotation speed evaluation stage (79) over said data bus (14).

11. An input-output unit for an operation control system containing a microprocessor, as defined in claim 8, wherein said shaft speed evaluation stage (79) is constituted in the form of a counter and in which a second frequency selecting circuit (116) is provided whereby the counting frequency of said last-mentioned counter is subject to being varied in response to commands received over said data bus (14), by said frequency selection decoder stage (119) when enabled by an output (74) of said decoding circuit (100).

12. An input-output unit for an operation control system containing a microprocessor, as defined in claim 7 or claim 11, wherein in which the respective frequency selection circuit (117, 116) is constituted by a frequency divider stage (115) provided for operation at a base counting frequency and producing therefrom a plurality of output frequencies, and a transfer switching device (116,117) provided for selection among siad putput frequencies of said frequency divider stage (115).

13. A input-output unit for an operation control system containing a microprocessor, as defined in claim 1, wherein at least one report-back gate (91) is provided that is connected with said data bus for transferring to said data bus data produced either internally or externally of said input-output unit or partly internally thereof and partly externally thereof.

14. An input-output unit for an operation control system containing a microprocessor, as defined in claim 13, wherein a buffer store (88, 90, 83, 70) is interposed in the input lead of at least one input of said report-back gate (91).

15. An input-output unit for an operation control system containing a microprocessor, as defined in claim 13, wherein at least one input of said report-back gate (91) is connected with a signal provided by a switch (38, 39).