Methods and apparatus for digitally signaling sounds and tones in a PCM multiplex system

• US 4,205,203 A
• Filed: 08/08/1978
• Issued: 05/27/1980
• Est. Priority Date: 08/08/1978
• Status: Expired due to Term

• Current Assignee: Wescom Switching Incorporated
• Original Assignee: Wescom Switching Incorporated
• Inventors: Pitroda, Satyan G., Vasanthkumar, Sagunabalan, Mehta, Madhu A.
• Primary Examiner(s): Stewart, David L.
• Application Number:
  US05/931,876
• Time in Patent Office: 658 Days
• Field of Search: 179/15 BY, 179/15 AT, 179/84 VF
• US Class Current: 370/525
• CPC Class Codes: H04Q 1/4575 which are transmitted in digital form

Abstract

Different ones of a plurality of sounds or tones are digitally signaled selectively in the different time slots of recurring frame cycles by initially storing a group of PCM samples for each sound in addressable memory. As each given time slot recurs one sample of a sound preselected for that time slot is read out to a common bus, and as successive cycles occur the address signals applied to the memory during any given time slot are progressively changed to cause repeated scanning of the samples of the preselected sound. After address signals for one time slot have been pulled from a read/write memory, they are replaced by writing "next sample address" signals into the same location of that memory, the latter having a word location for each time slot and being addressed for reading and writing by control signals which exist during and uniquely identify the successive time slots of each cycle. Different scan sequences for different sounds are created by modifying the formation of "next sample address" signals under the control of characteristic-representing signals stored in a sequence memory and read out by call signals representing the preselected sound for any time slot.

The preselection permits any of the sounds to be placed in any of the time slots or channels, but in the preferred form some of the time slots always carry the same sounds (fixed tones) while others may have their carried tones ("switched" or register tones) changed by commands received asynchronously from a central control unit.

The methods and apparatus utilize ROM (although RAM may be employed) to pair different ones of the several sounds with different ones of several on/off schedules to form a larger plurality of distinctive "tones", any one of which may be digitally signaled in any time slot or channel.

The method and the apparatus permit some of the tones to be "intercept" tones formed by two sounds transmitted alternately with a predetermined duty cycle.

Claims

1. The method of digitally signaling different ones of a plurality of sounds SD_o -SD_n in different ones of a plurality of successive time slots TS_o -TS_n of repeating cycles in a PCM multiplex communication system, said method comprising

(a) for each sound SD_o -SD_n initially storing in addressable, readable main memory--as multi-bit digital numerical words--a pattern of successive samples representing the sampled magnitudes of at least a symmetrical portion of an analog wave corresponding to the desired sound,

(b) during and only within the duration of each time slot, applying address signals to said main memory to effect readout to a common bus of one sample of a preselected pattern for that slot, and

(c) as each cycle transpires, changing the address signals so applied during each time slot so that the samples of the preselected pattern are scanned with the passage of on-going cycles.

2. The method set out in claim 1, further characterized in that during and within the duration of each time slot an on/off control signal is created at a first or second level, and readout to said common bus during predetermined ones of said time slots, corresponding to those in which the control signal is at its second level, is prevented, the control signal during a given slot existing at said second level during that same slot over a span of several cycles to define an "off" interval for the sound otherwise carried in that given slot, the "off" intervals of alternate on/off periods of time exceeding the cycle time by at least two orders of magnitude.

3. The method set out in claim 1 further including

(d) from time-to-time changing the preselected pattern of which a sample is read-out by the performance of said step (c), whereby different sounds are switched into a given time slot.

4. The method set out in claim 2 wherein different ones of a plurality of on/off schedules SCH_o -SCH_n are put into effect for different time slots.

5. The method set out in claim 1 further characterized by the additional procedures of

(d) producing during and only within the duration of the respective time slots tone ID signals identifying one of a plurality of tones TN_o -TN_n, each tone being characterized by a predesignated one of said sounds SD_o -SD_n paired with a predesignated one of a plurality of on-off schedules SCH_o -SCH_n, and

(e) utilizing said tone ID signals existing during any given time slot

(i) to make the preselected pattern referred to in said step (b) correspond to the predesignated sound of the identified tone, and

(ii) to prevent readout to said common bus during said given time slot during "off" intervals of an alternating on/off schedule which corresponds to the predesignated schedule of the identified tone.

6. The method set out in claim 1 wherein said step (c) includes using the address signals so applied during a given slot of a cycle C_i to derive the address signals so applied during the same slot of the next cycle C₁₊₁ to cause scanning and scan sequences of the samples in the pattern preselected for the given slot.

7. The method set out in claim 1 wherein said step (c) includes

(c'"'"') addressing a multi-word read/write memory according to the sequence of time slots to read said address signals, previously formed, to the address lines of said main memory, and

(c") before the next occurrence of the same time slot, writing into the word location so read signals representing the next address to be read in main memory during the next occurrence of the same time slot.

8. The method of digitally signaling a sound on an output bus in a PCM time multiplex system for transmission in a given one of successive time slots of repetitive time frames or cycles, the sound corresponding to a repeating analog wave, said method comprising

(a) initially storing in respective word locations of an addressable, readable main memory--as multi-bit digital numerical values--successive magnitude samples S_o -S_n of said wave,

(b) applying to the address lines of said main memory, during said given time slot of given cycle C_i, signals representing the address of one sample S_j and placing the readout signals from the main memory onto the output bus,

(c) using said address signals so applied to derive a next sample set of address signals, and

(d) repeating said steps (b) and (c) once for each of succeeding cycles C_i+1, C_i+2 . . . with the next sample set of address signals S_j+1, S_j+2 formed by step (c) employed as the signals applied in step (b) to said address lines.

9. The method of digitally signaling a sound on an output bus in a PCM time multiplex system for transmission in a given one of successive time slots of repetitive time frames or cycles, the sound corresponding to a repeating analog wave, said method comprising

(a) initially storing in respective word locations of an addressable, readable main memory--as multi-bit digital numerical values--successive magnitude samples S_o -S_n of said wave,

(b) providing in storage preformed sample address signals,

(c) during a given cycle C_i and a given time slot therein

(i) pulling from storage the preformed sample address signals and applying them to the address lines of said main memory to read out to said bus signals representing one of said samples S_j,

(ii) using the signals previously pulled from storage, and representing the address in main memory of a sample S_j, to derive and put into storage newly formed sample address signals representing the address of the next sample S_j+1 to be used, and

(d) repeating said step (c) during the same time slot of successive cycles C_i+1, C_i+2 . . . using successively for sub-step (i) the newly formed sample address signals created by sub-step (ii), so that the samples S_o -S_n are scanned and outputted in a desired sequence.

10. The method set out in claim 9 wherein said step (a) includes

(a'"'"') initially storing said successive samples at numerically ascending or descending addresses in said main memory,

and said sub-step (ii) includes

(ii'"'"') numerically changing by one the signals previously pulled from storage to derive the newly formed sample address signals,

whereupon the samples S_o -S_n are serially scanned in one of (1) first-to-last order or (2) last-to-first order.

11. The method set out in claim 9 further including

(e) detecting when the signals pulled from storage represent the address in main memory of the last sample in the plurality of samples S_o -S_n,

and in response to such detection, carrying out said sub-step (ii) by deriving said newly formed sample address signals to make them represent the address in main memory of one of the following:

(x) the first sample

(y) the next-to-last sample

(z) the last sample.

12. The method set out in claim 9 further including

(a) detecting when the signals pulled from storage represent the address in main memory of the first sample in the plurality of samples S_o -S_n,

and in response to such detection, carrying out said sub-step (ii) by deriving newly formed sample address signals to make them represent the address in main memory of the second sample.

13. The method set out in claim 9 further characterized in that said step (a) includes

(a'"'"') initially storing said successive samples at respective numerically ascending addresses in said main memory,

and said sub-step (ii) includes deriving said newly formed sample address signals by adding one to the signals previously pulled from storage.

14. The method of digitally signaling a sound on an output bus in a PCM time multiplex system for transmission in a given one of successive time slots of repetitive time frames or cycles, the sound corresponding to a repeating analog wave, said method comprising

(a) storing in respective word locations of an addressable, readable main memory, as multi-bit digital numerical values, successive magnitude samples S_o -S_n of said wave,

(b) providing preformed address signals in a next sample memory,

(c) during a given cycle C_i, and during a given time slot therein, reading said preformed address signals from said next sample memory onto the address lines of said main memory to cause readout of one sample S_j onto said output bus,

(d) using said address signals read out during said given cycle C_i to derive a next set of address signals which designate the main memory address of the next sample S_j+1 to be read,

(e) storing such next set in said next sample memory in place of the previous preformed address signals, whereby such next set becomes a new set of preformed address signals, and

(f) repeating said steps (c), (d) and (e) as recurring cycles transpire.

15. The method set out in claim 14 further characterized in that said steps (d) and (e) include

(e'"'"') detecting when the said address signals read-out from said next sample memory during the given time slot of any cycle represent the word location in said main memory of the last sample S_n, and in response to such detection deriving the next set of address signals to initiate a new scan of the stored samples.

16. The method set out in claim 14 further characterized in that said steps (d) and (e) include

(e'"'"') detecting when the said address signals read-out from said next sample memory during the given time slot of any cycle represent the word location in said main memory of the first sample S_o, and in response to such detection deriving the next set of address signals to represent the second sample S₁.

17. The method of digitally signaling different ones of a plurality of sounds SD_o -SD_n on a common output bus during different ones of time slots TS_o -TS_n within repeating cycles in a PCM time multiplex communication system, each sound corresponding to a different repeating analog wave, said method comprising

(a) storing in individual multi-word blocks of addressable, readable main memory--and as multi-bit digital numerical values--a pattern of successive magnitude samples S_o -S_n of respective ones of said waves,

(b) providing a read/write memory with a plurality of addressable word locations respectively corresponding to said time slots TS_o -TS_n, and storing in such word locations preformed address signals corresponding to the addresses of said main memory at which are located a given sample S_j of a pattern preselected to be signaled during the respective timeslots TS_o -TS_n,

(c) creating control signals CT_o -CT_n which exist during and identify successive time slots of each cycle, and which correspond to the different word locations of said read/write memory,

(d) applying said control signals to the address inputs of said read/write memory to cause readout therefrom of the respective preformed address signals during respective ones of the time slots in a given cycle C_i,

(e) applying the readout signals from said read/write memory to the address lines of said main memory to cause readout of one sample onto said output bus, a sample S_j of the pattern preselected for each time slot being outputted to the bus during that time slot within cycle C_i,

(f) prior to the occurrence of each time slot in the succeeding cycle C_i+1, utilizing the preformed address signals existing during each time slot of cycle C_i to derive new address signals representing the location in main memory of the next sample S_j+1 to be outputted for the pattern preselected to be signaled in that time slot,

(g) prior to the occurrence of each time slot in the succeeding cycle C_i+1, writing and storing into said read/write memory the new address signals derived by step (e), such that the previous preformed address signals are replaced by the new address signals in the word locations of read/write memory corresponding to the respective time slots TS_o -TS_n, and

(h) continuing said step (c) and repeating said steps (d) through (g) so that the samples for each sound to be signaled in each time slot TS_o -TS_n are successive outputted with scanning as recurring cycles transpire.

18. The method set out in claim 17 further including

(g'"'"') from time-to-time writing--to a location corresponding to a given time slot in said read/write memory--address signals designating the location of the first sample of a different sound, whereby the preselected sound signaled in the given time slot may be changed.

19. The method set out in claim 17 further characterized in that said step (f) includes

(f'"'"') detecting when the address signals read from said read/write memory during any given time slot represent the location in main memory of the last sample S_n for the sound being signaled in that time slot, and in response to such detection deriving the new address signals to initiate a new scan of the stored samples for that sound.

20. The method set out in claim 17 further characterized in that said step (f) includes

(f'"'"') detecting when the address signals read from said read/write memory during any time slot represent the address in main memory of the first sample S_o for the sound being signaled in that time slot, and in response to such detection deriving, the new address signals to initiate a new scan of the stored samples for that sound.

21. The method set out in claim 20 further characterized in that said step (f'"'"') includes

(f") storing in a readable first-sample memory address signals representing the first sample location in said main memory for each of the sounds SD_o -SD_n,

(f'"'"'") applying to the address lines of said first-sample memory, during each time slot, signals which cause readout of the first sample address signals for the sound being signaled in that time slot, and

(f"") comparing said readout of the first sample address signals with the address signals read from said read/write memory to detect when the address signals read from said read/write memory represent the location in main memory of the first sample S_o.

22. The method of signaling different ones of a plurality of sounds SD_o -SD_n on a bus in desired ones of a plurality of time slots TS_o -TS_n in a PCM time multiplex communication system, said method comprising

(a) for each of said sounds SD_o -SD_n, initially storing in addressable main memory, as multi-bit numerical values, a pattern PT_o -PT_n of samples of at least a symmetrical portion of an analog wave representing that sound, each sample having a unique memory address location, and said main memory having a common output bus,

(b) producing in time sequence different control signals CT_o -CT_n which respectively exist during and uniquely identify different ones of said time slots, such control signals recurring in repetitive cycles, and

(c) utilizing each of said control signals CT_o -CN_n to create one set of address signals SAO-7 which respectively exist only during and within duration of each of said time slots, each set of address signals being applied to said main memory to cause reading from said memory onto said output bus one sample of one pattern PT_z,the pattern PT_z being preselected for digital transmission in the respective time slot identified by that control signal.

23. The method set out in claim 22, wherein there are a plurality of sounds SD_o -SD_n each represented by a pattern PT_o -PT_n of stored samples S_o -S_n in main memory and further including

(d) utilizing each control signal during successive cycles C_i, C_i+1, C_i+2 . . . to cause reading from main memory onto said bus successive samples S_j, S_j+1, S_j+2 . . . of a preselected pattern PT_z such that as a given control signal CT_y for a given slot TS_y recurs, the samples S_o -S_n of the preselected pattern are successively applied to said bus.

24. The method set out in claim 23, further characterized in that the plurality of samples S_o -S_n in the pattern PT_z are repeatedlyscanned and applied to said bus in a predetermined scan sequence as the number of repeating cycles exceeds the quantity of stored samples S_o -S_n in the preselected pattern.

25. The method set out in claim 23 further including

(e) producing an on/off signal which during the existence of each control signal has first and second values over extended time intervals of p and q seconds, where p and q form a preselected one of a plurality of on/off schedules SCH_o -SCH_n, and

(f) gating or blocking sample signals from said main memory to or from said bus when said on/off signal respectively has said first or second value.

26. The method set out in claim 25 further including

(g) generating a plurality of schedule signals each corresponding to one of said schedules SCH_o -SCH_n and having a different high/low, on/off time duty cycle, and

(h) during the existence of each of the control signals CT_o -CT_n, utilizing a preselected one of said schedule signals as said on/off signal to control gating of signals from the output of the main memory.

27. The method set out in claim 25, wherein any one of the sounds SD_o -SD_n with any one of the schedules SCH_o -SCH_n forms one of a plurality of tones TN_o -TN_n which may be transmitted in any one of the time slots TS_o -TS_n, and further characterized by

(g) storing in pattern-select memory at addressable locations digital words respectively identifying predetermined ones of the patterns PT_o -PT_n,

(h) storing in schedule-select memory at addressable locations digital words respectively identifying predetermined ones of the individual schedules SCH_o -SCH_n,

the pattern and the schedule identifications PT_z and SCH_u stored at the same address locations in said two select memories forming in combination a particular one TN_x of the tones TN_o -TN_n,

(i) applying to both said pattern-select and schedule-select memories the same address signals, designating a preselected tone TN_x, during the existence of one control signal corresponding to a particular time slot TS_y to read out the stored words from such memories,

(j) utilizing said readout word from said schedule-select memory to make said on/off signal have corresponding p and q times according to the schedule SCH_u, and

(k) utilizing the readout word from said pattern-select memory during each time slot TS_y to cause application of a sample of the pattern PT₂ to said bus under the gating control of said on/off signal.

28. The method set out in claim 22, further characterized in that said step (c) includes

(c'"'"') applying said control signals CT_o -CT_n as address signals to a random access memory (RAM) to read out therefrom, as an address input to said main memory, a representation of the main memory location of the sample, within a preselected pattern, to be outputted during each time slot of a given cycle;

and during each such time slot, writing into the same address location of said RAM a multi-bit word representing the main memory address of the next sample, within the preselected pattern, to be outputted during the same time slot of the following cycle.

29. The method set out in claim 28, further characterized in that the preselected pattern PT_z to be transmitted digitally in any given time slot is preselected by writing into said RAM, at the address corresponding to said time slot, the main memory address number of a sample within the pattern PT_z.

30. The method set out in claim 29, further including

(d) initially storing the main memory address number for the first sample of each pattern PT_o -PT_n in an auxiliary readable memory (FS ROM) at an address which corresponds to an ID number for that pattern, and when a particular pattern PT_z is to be preselected for transmission in a given time slot, applying to the address lines of said auxiliary memory signals representing the corresponding ID number during the existence of said control signals representing the given time slot, and

(e) writing into said RAM the output of said auxiliary memory at an address corresponding to the control signals.

31. The method set out in claim 22, further characterized in that said control signals are produced by a counter and including driving the counter to increment its count states during each of said time slots, said counter executing one repetitive counting cycle for each cycle.

32. The method of signaling any of various ones of a plurality of sounds SD_o -SD_n in any of a plurality of time slots TS_o -TS_n of successive cycles in a PCM multiplex communications system, said method comprising

(a) for each of the sounds SD_o -SD_n, initially storing, in addressable word locations of a main readable memory, the successive digital multi-bit samples which represent that sound,

(b) creating control signals CT_o -CT_n which exist during and uniquely identify each of the time slots TS_o -TS_n in a cycle,

(c) from time-to-time, creating paired command signals in which each pair represents (i) a commanded one of the plurality of sounds SD_o -SD_n and (ii) a commanded one of the time slots TS_o -TS_n in which that commanded one sound is to be signaled,

(d) in response to the appearance of a pair of command signals, storing the commanded sound signal in a read/write sound-select memory at an address corresponding to and determined by the commanded time slot signal,

(e) applying said control signals to the address lines of said sound-select memory to read out therefrom during successive time slots the respective commanded sound signals previously stored,

(f) utilizing said readout commanded sound signals to form, during each time slot when commanded sound signals exist, address signals representing the location in said main memory of one sample of the multiple samples for the sound that corresponds to the commanded sound signals,

(g) applying said address signals to said main memory, and

(h) changing the address signals so formed during any given slot from cycle to cycle to scan the samples representing the commanded sound for that slot.

33. The method of signaling various ones of a plurality of tones in different desired ones of a plurality of time slots of successive cycles in a PCM multiplex communication system, said method comprising

(a) initially storing in addressable main memory, for each of a plurality of tones, successive multi-bit digital samples representing successive magnitudes of the tone sound,

(b) creating control signals CT_o -CT_n which respectively exist during and uniquely identify a plurality of time slots in a cycle,

(c) from time-to-time, creating paired command signals which respectively represent (i) a commanded one of a plurality of tones TN_o -TN_n and (ii) a commanded one of the time slots TS_o -TS_n in which the commanded tone is to be signaled,

(d) storing the commanded tone signals in a read/write tone select memory at an address location represented and determined by the paired commanded time slot signals, said tone select memory having an addressable word location for each of the time slots,

(e) applying said control signals to the address lines of said tone select memory to read therefrom during different time slots of each cycle the respective previously stored commanded tone signals for respective ones of the time slots,

(f) utilizing the readout commanded tone signals to create, during each of said time slots, address signals which represent the address in said main memory of one of the samples there stored for the tone sound called for by said commanded tone signals, and

(g) thereafter incrementing or decrementing the address signals applied to said main memory during the respective time slots of each cycle, so that the successive samples for a commanded sound are scanned and outputted during the same, commanded time slot of successive cycles.

34. The method of digitally signaling fixed and switchable sounds in a PCM multiplex communication system, comprising

(a) producing control signals CT_o -CT_n which exist respectively during and uniquely identify each of successive time slots TS_o -TS_n of repeating cycles,

(b) initially storing a pattern of samples for each of a corresponding plurality of sounds SD_o -SD_n in addressable, readable main memory, each pattern of samples representing, as multi-bit digital words, the successive sample magnitudes of a recurring analog wave which corresponds to a desired sound,

(c) utilizing a first sub-plurality of said control signals CT_o -CT_n to cause readout, from main memory to a common bus, of one sample of respective pre-assigned sounds, with the samples for a given sound being progressively scanned during the same time slot of successive cycles, whereby the respective pre-assigned sounds are transmitted in the time slots corresponding to said first sub-plurality of control signals in every cycle,

(d) utilizing a second sub-plurality of said control signals as address inputs to a read/write memory to cause readout of sound ID signals from memory locations respectively corresponding to the values of said control signals during the corresponding time slots,

(e) from time-to-time, producing pairs of command signals with each pair comprising (i) sound command sound ID signals and (ii) time slot command signals equal to one of said second sub-plurality;

and applying the sound command ID signals to the input data lines with application of said time slot command signals to the address lines of said read/write memory to cause writing into the latter, and

(f) utilizing the readout sound ID signals, as produced according to said step (d), to cause readout, from main memory to said common bus, during the time slot when said readout sound ID signals appear, of one sample for the sound identified by such ID signals, with the samples for a given sound being progressively scanned during the same time slot of successive cycles,

whereby any one of the sounds may be carried in any one of the channel time slots which correspond to said second sub-plurality of control signals, as determined by the writing of command sound ID signals into locations of said read/write memory at addresses represented by the paired time slot command signals.

35. The method of forming and digitally transmitting on an output bus any one of a plurality of tones TN_o -TN_n, where each tone is constituted by one of a plurality of sounds SD_o -SD_n modulated with any one of a plurality of on/off schedules SCH_o -SCH_n, in a PCM time multiplex system, said method comprising

(a) for each of said sounds SD_o -SD_n, initially storing in addressable main memory, as multi-bit numerical values, a pattern of successive samples of at least a symmetrical portion of an analog wave representing that sound, each numerical sample having a unique memory address location,

(b) storing in sound-select memory at addressable locations preselected ones of ID words PI_o -PI_n respectively identifying the sounds SD_o -SD_n,

(c) storing in schedule-select memory at addressable locations preselected ones of schedule ID words SCI_o -SCI_n respectively identifying the schedules SCH_o -SCH_n,

the pairing of a sound ID PI_x word with a schedule ID word SCI_x at corresponding address locations in said two select memories designating a particular tone TN_x,

(d) applying during different time slots TS_o -TS_n of repetitive cycles different ones of tone ID signals TI_o -TI_n to the address lines of both said sound and schedule select memories, whereby during different time slots different predetermined pairs of ID words PI_x and SCI_x are signaled at the outputs of such memories,

(e) utilizing the SCI_x word signals existing during any of said time slots to create a gating signal which exists at on and off levels respectively during that slot over intervals of p and q seconds and which form an on/off schedule SCH_x corresponding to the identification word SCI_x,

(f) utilizing said PI_x word signals existing during any of said time slots to create and apply, to the address inputs of said main memory, signals which cause readout from main memory one sample forming part of the representation of the sound SD_x identified by said PI_x word signals, and

(g) applying or blocking the sample signals so read-out respectively to or from an output bus when the gating signal contemporaneously is on or off, respectively.

36. The method set out in claim 35 wherein said step (f) includes reading out successive samples of the sound SD_x during the same time slot of successive cycles, with repetitive scanning of all such samples taken one at a time.

37. The method set out in claim 35 wherein said step (d) includes

(d1) selectively changing the tone ID signals applied during different time slots to the address lines of said sound and schedule select memories, thereby to preselect and "switch" different desired tones into particular time slots.

38. The method set out in claim 35 further including

(h) storing in on/off memory strings of bits each corresponding to one of said schedules SCH_o -SCH_n, said stored bits of each string being a different combination of 1'"'"'s and 0'"'"'s, with any given string containing n 1'"'"'s in succession when an "on" interval of nΔ

T is desired, and m 0'"'"'s in succession when an "off" interval of mΔ

T is desired, in the schedule corresponding to that given string,

(i) reading said on/off memory in a repetitive rollover sequence of its addresses at a rate of one address per interval Δ

T, to produce at its output bi-state signals respectively corresponding to the strings of stored bits, and

(j) utilizing any of said signaled schedule ID words SCI_o -SCI_n to select the corresponding one of the bi-state signals for use as said gating signal.

39. The method of digitally transmitting different sounds on an output bus in a PCM time multiplex communication system, said method comprising

(a) for each of said sounds, storing in an addressable memory block--as multi-bit numerical values--successive samples of at least a symmetrical portion of an analog wave representing that sound,

(a1) the stored samples for each sound constituting a set,

(a2) the quantities of samples in at least some of said sets being unequal,

(a3) each of said blocks having a quantity of word locations which is equal to or greater than the quantity of samples stored in that block, and all blocks having output lines coupled to a common output bus,

(a4) said sets being stored in their respective blocks such that the last sample of every set is stored at the same, common addressable word location within a block, and with the samples of each set in sequential rollover order,

(b) enabling the reading from one preselected block during the same given time slot within every repetitive cycle of time slots,

(c) applying to the address line inputs of all blocks sample select signals which represent, during the same time slot of successive cycles, successive sample addresses within the enabled block, to read out onto said bus signals corresponding to successive samples of a selected sound during a selected time slot of successive cycles, the samples of a set thus being read out in a scanned sequence,

(d) monitoring the sample select signals to detect when they represent said common addressable word location, and

(e) in response to such detection, changing the sample select signals produced during the ensuing cycle to begin a new scan of the samples in the preselected block during the given time slot of later cycles.

40. The method set forth in claim 39, further including

(f) during the given time slot of any cycle said detection does not occur, changing said sample select signals to represent the word address of the next sample in a seriatim scan of the samples.

41. The method set forth in claim 39 wherein the samples in any given block are scanned in different fashions during successive passes, and said step (e) includes

(e'"'"') in response to said detection, changing the sample select signals produced during the given time slot of following cycles to produce the desired scan fashion for the following pass.

42. The method set forth in claim 39 wherein said step (d) includes

(d'"'"') during every time slot of every cycle, applying the sample select signals to common decoding apparatus which produces a signal (255) indicating that such sample select signals represent said common addressable word location and that the last sample of a set is being read.

43. The method set out in claim 39 wherein said step (a) is further characterized in that the last sample of every set is stored in the last (highest address) word location (255) of its memory block, and the samples in a set are normally scanned seriatim from the first sample word location to last sample word location of a memory block.

44. The method set out in claim 39 wherein step (e) includes

(e'"'"') in response to such detection, changing the sample select signals, produced during the given time slot of the ensuing cycle, to represent the address of the first sample stored in the selected block so that the new scan is in the normal first-to-last sample fashion.

45. The method set out in claim 39 wherein said step (e) includes

(e'"'"') changing the sample select signals, produced during the selected time slot of the ensuing cycle, to represent the address of the next-to-last sample stored in the selected block, and in the same time slot of following cycles changing the sample select signals successively to cause readout of the samples in reverse sequence during the given time slot of successive cycles until the first sample has been read out, thereby making the new scan a reverse order scan.

46. The method set out in claim 39 wherein said step (e) includes

(e'"'"') in response to such detection, making the sample select signals produced during the given time slot of the ensuing cycle following such detection the same as those produced during the cycle in which such detection occurs, so that the output of the last sample is repeated at the beginning of the new scan.

47. The method set out in claim 39 wherein said step (e) includes

(e'"'"') in response to such detection, complementing the sign bit of all samples read out to said bus during the new scan.

48. The method set out in claim 44 further including complementing the sign bit of all samples read out to said bus during the new scan.

49. The method set out in claim 45 further including complementing the sign bit of all samples read out to said bus during the new scan.

50. The method set out in claim 46, further including reading the samples of the selected block in reverse address order after the last sample has been repeated at the beginning of the new scan.

51. The method set out in claim 39 wherein said step (a) is further characterized in that the last sample of every set is stored in the first (lowest address) word location (000) of its memory block, and a normal scan of the samples in a set is from the first sample location (at the highest address used in the block) through progressively lower address locations to the first word location.

52. In the digital signaling of sounds in a PCM multiplex communication system, the method of outputting successive digital samples of a sound, said method comprising

(a) initially storing in successive address locations of addressable, readable main memory--as multi-bit digital words--successive samples S_o -S_n representing successive sampled magnitudes of at least a symmetrical portion of a cyclic analog wave corresponding to the desired sound,

(b) producing character signals which represent the characteristic of the necessary sequences of successive scans of said samples which will recreate the analog wave in PCM form,

(c) during a given time slot in recurring cycles, applying to the address lines of said main memory address signals to effect readout of one sample S_j,

(d) changing said address signals prior to the next occurrence of the given time slot, to represent the address of the next sample to be read out, so that the samples are scanned seriatim,

(e) detecting when said address signals represent the address of the last sample S_n, and

(f) in response to such detection, using said character signals to determine the succeeding value to be given to said address signals for readout of the next sample at the beginning of a new scan.

53. The method set out in claim 52, wherein said character signals designate that the samples are to be repeatedly scanned in first-to-last order, and said step (f) includes

(f'"'"') making the succeeding value of said address signals represent the address of the first sample.

54. The method set out in claim 52, wherein said character signals designate that the samples are to be scanned alternately in read-up and read-down address order, and said steps (f) and (d) include

(f'"'"') making the succeeding value of said address signals represent the address of the next-to-last sample S_n-1, and

(d'"'"') during the ensuing scan of the samples decrementing said address signals to scan in read-up address order.

55. The method set out in claim 52 wherein said character signals designate that the last sample is to be repeated after having been read out once, and said step (f) includes

(f'"'"') making the succeeding value of said address signals represent the same last sample address, and thereafter prior to the next occurrence of the given time slot forming the next-succeeding value to be given to said address signals to proceed with a new scan.

56. The method set out in claim 52 wherein said character signals designate that the samples are to be read-out with alternately changed signs during successive scans, and said step (f) includes

(f'"'"') complementing the sign bit of the sample read-out signals during the ensuing scan of samples.

57. The method set out in claim 54 further including the step of

(g) during a scan of the samples in read-up address order, detecting when said address signals represent the address of the first sample S_o, and

(h) in response to such detecting making the address signals during the subsequent occurrences of said given time slot progressively increment until they represent the address of the last sample S_n and the last sample is read out.

58. The method of digitally signaling different ones of sounds SD_o -SD_n in different time slots TS_o -TS_n successive cycles in a PCM time multiplex system, said method comprising

(a) for each sound SD_o -SD_n, initially storing in a group of successive addressable word locations of addressable, readable main memory--as multi-bit digital words--successive samples S_o -S_n representing the successive sample magnitudes of at least a symmetrical portion of a cyclic analog wave corresponding to the sound to be reproduced,

(b) producing control signals CT_o -CT_n which respectively exist during and uniquely identify different time slots within each recurring cycle,

(c) during different time slots, using said control signals to create address signals applied to said main memory to effect readout onto a common bus of one sample of a preselected one of said sounds assigned to the respective time slots,

(d) from cycle-to-cycle changing the address signals created during each of said different time slots to successively scan the samples of the sound preselected for that time slot, some of sounds SD_o -SD_n being represented by stored sample patterns in said main memory which require different scan sequences, such for example as (i) first-to-last;

(ii) first-to-last, last-to-first, first-to-last;

(iii) last sample repeat; and

(iv) sample-signs-true, sample-signs-complemented,

(e) storing, in separate word locations of addressable, readable SEQ memory, scan sequence characteristic signals for each of the respective sounds SD_o -SD_n,

(f) applying to the address lines of saidm SEQ memory, during each of said different time slots, call signals which will effect read-out of the cahracteristic signals for the particular sound preselected for that time slot, and

(g) utilizing said characteristic signals to govern the changing of the address signals in order to produce scan sequences which conform to the requirements of the sound preselected for each of said different time slots.

59. The method set out in claim 58 wherein the scan sequence characteristics of certain ones of the sounds SD_o -SD_n require that the sound samples be repeatedly scanned in first-to-last order, and in any time slot when any such sound is the preselected sound, the output from said SEQ memory causes said step (g) to include

(g'"'"') changing the address signals in first-to-last order until they represent the address of the last sample S_n of the preselected sound, then changing the address signals to represent the address of the first sample S_o, and then resuming the changing in first-to-last order.

60. The method set out in claim 58 wherein the scan sequence characteristics of certain ones of the sounds SD_o -SD_n require that the sound samples be scanned alternately in first-to-last and last-to-first order, and in any time slot when any such sound is the preselected sound, the output from said SEQ memory is utilized to cause said step (g) to include

(g'"'"') changing the address signals in first-to-last order until they represent the address of the last sample S_n of the preselected sound, then changing the address signals in last-to-first order until they represent the address of the first sample S_o.

61. The method set out in claim 58 wherein the scan sequence characteristics of certain ones of the sounds SD_o -SD_n require that the sound samples be scanned, with the last sample repeated following a first-to-last scan, and in any time slot when any such sound is the preselected sound, the output from said SEQ memory is utilized to cause said step (g) to include

(g'"'"') changing the address signals in first-to-last order until they represent the address of the last sample S_n of the preselected sound, maintaining the address signals unchanged during the next succeeding occurrence of the given time slot, and thereafter changing the address signals to proceed with the next scan in conformance with the requirements of the sound preselected for that time slot.

62. The method set out in claim 58 wherein the scan sequence characteristics of certain ones of the sounds SD_o -SD_n require that the sound samples be scanned with the samples being applied to said common bus with changed signs during alternate ones of successive scans, and in any time slot when any such sound is the preselected sound, the output from said SEQ memory is utilized to cause said step (g) to include

(g'"'"') detecting when said address signals represent the address of the last sample S_n at the end of a first-to-last scan or when they represent the address of the first sample S_o at the end of a last-to-first scan, and

(g") in response to such detection, complementing the sign bit of the sample read-out signals before they are applied to said common bus during the ensuing scan of the samples.

63. The method of digitally signaling an intercept type tone in a PCM multiplex communication system wherein a given time slot appears in each of on-going cycles recurring at a given rate (e.g., every 125 μ

sec.), said method comprising

(a) initially storing in at least two blocks of a readable main memory at least two respective patterns P_a and P_b each made up of an equal plurality of samples S_o -S_n which digitally represent numerically the successive magnitudes of at least two respective sounds SD_a and SD_b,

(b) during and only within the duration of each occurrence of the given time slot, normally applying to the address lines of said memory signals which represent the address of a sample S_j in the pattern P_a, and in successive cycles C_i, C_i+1, C_i+2 . . . changing such signals such that the samples S_o -S_n are read out in a scanned order S_j, S_j+1, S_j+2 . . . , and

(c) during alternate ones of successive time intervals occurring in succession at a rate substantially lower than said given rate, converting the address-representing signals produced according to step (b) so that they represent a sample S_j in the pattern P_b, and so that the samples S_o -S_n of the pattern P_b are read out in a scanned order.

64. The method of digitally signaling an intercept tone in a PMC multiplex communication system, comprising

(a) initially storing, in addressable main memory as multi-bit digital words, successive samples for two sounds, the samples for both sounds being equal in quantity and being stored in respective corresponding words within each block being addressable by a first plurality of lower order bit signals and the two blocks being individually addressable by a 0 or 1 level in a higher order bit signal,

(b) producing a periodically recurring time slot signal CT_x,

(c) producing lower order bit signals representing an address number for a word within a block, and during each recurrence of said time slot signal CT_x

(i) applying said address number signals to the address lines of both of said memory blocks,

(ii) modifying said address number signals to call for the next word location in a scanning sequence, and

(d) producing an alternating signal which alternates between 0 and 1 level with a periodicity substantially greater than that of said time slot signal, and

(e) applying said alternating signal to said memory as a higher order address bit to alternately address the adjacent blocks,

whereby the output signals from said main memory represent successive samples of a first sound for a first time interval and the successive samples of a second sound for a second time interval, the first and second intervals recurring alternately, to form a digital signaling of an "intercept" sound.

65. The method set out in claim 64 further characterized by the step of holding said alternating signal steadily at a 0 or 1 level when it is desired to make the output signals from said memory represent only the first or the second sound.

66. The method set out in claim 64 wherein each memory block is part of a memory having plural blocks of 256 words, the words within each block being addressable by lower binary address signals xxxxxxxx representing decimal values of 0 to 255, and the blocks are addressable by higher order bit values y in a complete address signal yyy₁ xxxxxxxx, said alternating signal forming the higher order address bit signal y₁.

67. The method of digitally signaling different sounds in different time slots of recurring frame cycles in a PCM multiplex communication system, comprising

(a) initially storing, in addressable, readable main memory as multi-bit digital words, successive samples S_o -S_n in each of a plurality of patterns PT_o -PT_n corresponding to a plurality of sounds SD_o -SD_n, the samples of each pattern being stored in respective blocks of N memory words such that sample S_i of pattern PT_z is addressable by lower order address bits of a certain combination, with a higher order address bit b_n =0, and sample S_i of pattern PT_z+1 is addressable by the same certain combination of lower order address bits with the higher order address bit b_n =1,

(b) initially storing, in respective word locations of addressable readable pattern-select memory, different desired ones of a plurality of pattern ID signals PI_o -PI_n represented by a predetermined number (n-1) of bits, with certain ones of said stored ID signals containing a 1 in an nth bit place,

(c) producing control signals CT_o -CT_n which exist respectively during and uniquely identify successive time TS_o -TS_n of repeating frame cycles,

(d) during the presence of each control signal CT_o -CT_n, reading out one of the stored pattern ID signals from said sound-select memory,

(e) utilizing the (n-1) bits of a pattern ID signal PI_z so read-out to create, and apply to the address lines of said main memory , multi-bit address signals which cause read-out, from main memory, of a sample S_j in the pattern PT_z, and changing said address signals incrementally from cycle to cycle so that the samples of pattern PT_z are scanned, and

(f) in response to the presence of a 1 in the nth bit place of any pattern ID signal PT_z so read out from said sound-select memory, periodically complementing the higher order address bit b_n in said multi-bit address signals so that samples from two patterns PT_z and PT_z+1 are read from main memory in a given time slot but in alternate ones of a succession of time intervals determined by the periodic complementing of the higher order address bit.

68. The method of creating different on/off schedules for a plurality of information signals which are ordinarily transmitted in respective time slots of successive cycles in a multiplex communication system, said method comprising

(a) initially storing strings of 0 and 1 bits in an addressable memory for each of a plurality of on/off schedules, each string containing N bits and being characterized by n 1'"'"'s in succession followed by m 0'"'"'s in succession, where n and m are integers including zero but not exceeding N,

(b) reading out from said memory simultaneously on plural output lines one bit of each string, and continuing such reading to cyclically scan at a predetermined rate (e.g., one readout per 50 m.s.) all the successive bits of all the stored strings,

(c) during certain time slots within successive cycles selecting from the output lines of said memory one readout string of signals, and

(d) gating to or blocking from a common output bus the information signals arriving in any given time slot only when the selected readout string of signals has respectively one or the other of its two possible states during that time slot.

69. The method set out in claim 68 further characterized in that said cycles have a duration on the order of 125 μ

seconds and the successive reading-out from said memory occurs for intervals on the order of 50 m.s. with negligible spacing between such intervals.

70. The method set out in claim 68 further characterized in that said memory contains N addressable word locations, with each word containing one bit of each string, and the cylical scanning of said step (d) is carried out by driving a digital rollover counter from regularly recurring clock pulses, said counter having N possible count states, and applying the multi-bit output of said counter to the address input lines of said memory.

71. The method set out in claim 68 wherein said step (c) includes

(c'"'"') initially storing a schedule select code in each word location of an addressable schedule-sheet memory,

(c") applying to the address inputs of said schedule-select memory during each of certain time slots within successive cycles address signals which correspond to the particular code for the desired schedule to be created in that time slot, and

(c'"'"'") using the output of said schedule select memory during each time slot to select one string of output signals read out from said string-storing memory.

72. Apparatus for digitally signaling different ones of a plurality of sounds SD_o -SD_n in different ones of a plurality of successive time slots TS_o -TS_n of repeating cycles in a PCM multiplex communication system, said apparatus comprising, in combination

(a) a multi-word addressable, readable main memory storing--as multi-bit digital numerical words--patterns PT_o -PT_n corresponding to each sound, with each pattern formed by a plurality of successive samples at successive addresses and representing the sampled magnitudes of at least a symmetrical portion of an analog wave corresponding to the desired sound,

(b) means for applying to the address lines of said main memory, during and only within the duration of certain time slots, address signals to effect readout to a common bus of one sample of a preselected pattern for that slot, and

(c) means for changing from cycle-to-cycle, the address signals so applied during each time slot so that the samples of the preselected pattern are scanned with the passage of on-going cycles.

73. The combination defined in claim 72 further including

(d) means for producing during and within the duration of some of said certain time slots a control signal at a first or second level, the control signal during a given slot existing at said second level over a span of several cycles to define an "off" interval for the sound otherwise carried in that given slot, and

(d) means responsive to the control signal for preventing readout to said common bus during those time slots in which the control signal is at its second level, the "off" intervals of alternate on/off periods of time exceeding the cycle time by at least two orders of magnitude.

74. The combination defined in claim 72 further including

(d) means for changing, from time-to-time, the preselected pattern of which a sample is read out by means (c), thereby to switch different sounds into a given time slot.

75. The combination set out in claim 73 wherein said means (d) includes

(d'"'"') means for changing, from time-to-time, the schedule of the on/off intervals of said on/off periods to conform to a preselected one of a plurality of on/off schedules SCH_o -SCH_n.

76. The combination defined in claim 72 further including

(d) means for producing, during and only within the duration of the said certain time slots, tone ID signals identifying one of a plurality of tones TN_o -TN_n, each tone being characterized by a predesignated one of said sounds SD_o -SD_n paired with a predesignated one of a plurality of on-off schedules SCH_o -SCH_n, and

(e) means responsive to said tone ID signals existing during any given time slot

(i) to make said means (d) apply to the address lines of said main memory, address signals to effect readout of one sample of the pattern corresponding to the characterized sound of the identified tone, and

(ii) to prevent readout to said common bus during said given time slot during "off" intervals of an alternating on/off schedule which corresponds to the characterized schedule of the identified tone.

77. The apparatus defined in claim 72, wherein said means (c) includes

(c'"'"') means responsive to the address signals applied to said main memory during any given slot of a cycle C_i to derive new address signals to be so applied during the same slot of the next cycle C_i+1, to cause scanning and scan sequences of the samples in the pattern preselected for the given slot.

78. The combination set out in claim 72, wherein said means (c) includes

(c'"'"') a multi-word read/write memory,

(c") means for addressing said read/write memory according to the sequence of time slots to read therefrom said address signals, previously formed, to the address lines of said main memory, and

(c'"'"'") means for writing, before the next occurrence of the same time slot, into said read/write memory at the word location so read, signals representing the next address to be read from main memory during the next occurrence of the same time slot.

79. For use in a PCM time multiplex system, apparatus for digitally signaling a sound on an output bus during a given one of successive time slots of repetitive time cycles, the sound corresponding to a repeating analog wave, said apparatus comprising in combination

(a) a multi-word addressable main memory formed to store and hold in respective word locations--as multi-bit digital numerical values--successive magnitude samples S_o -S_n of said wave,

(d) means for feeding to the address lines of said main memory, during said given slot of a given cycle C_i, address signals representing the address of one stored sample S_j which is then signaled at the main memory output bus,

(c) means responsive to said address signals so applied to derive a next sample set of address signals, and

(d) means for causing said means (b) to use and feed the next sample address signals during the given slot of the next cycle C₁₊₁, so that said samples are outputted in succession.

80. For use in a PCM time multiplex system, apparatus for digitally signaling a sound on an output bus during a given one of successive time slots of repetitive cycles, the sound corresponding to a repeating analog wave, said apparatus comprising, in combination

(a) an addressable, readable main memory storing in respective word locations--as multi-bit digital numerical values--successive magnitude samples S_o -S_n of said wave,

(b) storage means for holding address signals,

(c) means operative during the given time slot of any cycle C_i for applying said address signals to the address lines of said main memory to read to the output bus signals representing one of said samples S_j, and

(d) means responsive to and operative to use the address signals so applied during any cycle C_i, and representing the address in main memory of the sample S_j, to derive and place in said storage means

(b) newly formed address signals representing the address of a next sample S_j+1 to be next read out to said bus in a scan of the samples,

whereby during the given slot of cycles C_i, C_i+1, C_i+2 . . . samples S_j, S_j+1, S_j+2 . . . are successively read out to the bus.

81. The combination defined in claim 80 further characterized in that

(a'"'"') said main memory stores said successive samples at numerically ascending or descending address locations,

and said means (d) includes

(d'"'"') means for deriving the newly formed address signals by adding or subtracting one to the address signals so applied during any cycle C_i.

82. The combination defined in claim 80, further including

(e) means for producing a detection signal when the address signals so applied during any cycle C_i represent the address of the last sample in the plurality of samples S_o -S_n,

(f) means responsive to said detection signal to cause said means (d) to derive the newly formed address signals to represent the address of one of the following:

(i) the first sample,

(ii) the next-to-last sample,

(iii) the last sample,

83. Apparatus for use in signaling different ones of a plurality of sounds SD_o -SD_n on a bus in desired ones of a plurality of time slots TS_o -TS_n in a PCM time multiplex communication system, said apparatus comprising in combination

(a) an addressable, readable main memory storing, for each of said sounds SD_o -SD_n a pattern of PT_o -PT_n each constituted of successive binary samples of at least a symmetrical portion of an analog wave representing that sound, each sample having a unique memory address location, and said main memory having a common output bus,

(b) means for producing in time sequence different control signals CT_o -CT_n which exist respectively during and uniquely identify different ones of said time slots, such control signals recurring in repetitive cycles, and

(c) means responsive to each of said control signals CT_o -CT_n to apply to the address lines of said main memory address signals which cause reading onto said output bus one sample of one pattern PT_z, the pattern PT_z being preselected for digital transmission in the respective time slot identified by that control signal.

84. The combination defined in claim 83, wherein there are a plurality of sounds SD_o -SD_n respectively represented by patterns PT_o -PT_n of stored samples S_o -S_n in said main memory, and further including

(d) means responsive to each control signal during successive cycles C_i, C_i+1, C_i+2 . . . to cause said means (c) to apply to the address lines of said main memory address signals which cause reading onto said bus of successive samples S_j, S_j+1, S_j+2 . . . of a preselected pattern PT_z, such that as a given control signal CT_y recurs during successive cycles the samples S_o -S_n of the preselected pattern are successively applied to said bus.

85. The combination defined in claim 84, wherein said means (d) includes

(d'"'"') means for changing the address signals applied to the address lines of said main memory, during a given slot of successive cycles, so that the samples S_o -S_n of the preselected pattern PT_z for that slot are repeatedly scanned and applied to said bus in a predetermined scan sequence as the number of repeating cycles exceeds the quantity of stored samples in the preselected pattern.

86. The combination defined in claim 84 further including

(e) means producing an on/off signal which, during the existence of each control signal CT_o -CT_n and time slot TS_o -TS_n, has first and second values over extended time intervals of p and q seconds, where p and q form a preselected one of a plurality of on/off schedules SCH_o -SCH_n, and

(f) means for respectively gating or blocking sample output signals from said main memory to or from said bus when said on/off signal respectively has said first or second value.

87. The combination defined in claim 86 further including

(g) means for generating continuously a plurality of schedule signals each having a different high/low on/off time duty cycle corresponding to one of a plurality of schedules SCH_o -SCH_n, and

(h) said means (f) includes means responsive to each of the control signals CT_o -CT_n for controlling the application of output signals from said main memory to said bus according to the high/low timing of a preselected one of said schedule signals.

88. The combination defined in claim 86, wherein any one of the sounds SD_o -SD_n with any one of the schedules SCH_o -SCH_n forms one of a plurality of tones TN_o -TN_n which may be transmitted in any one of the time slots TS_o -TS_n, and further including

(g) a readable pattern-select memory storing at addressable locations digital words respectively identifying predetermined ones of the patterns PT_o -PT_n,

(h) a readable schedule-select memory storing at addressable locations digital words respectively identifying predetermined ones of the individual schedules SCH_o -SCH_n,

the pattern and the schedule identifications PT_z and SCH_u stored at the same address locations in said two select memories forming in combination a particular one TN_x of the tones TN_o -TN_n,

(i) means for applying to the address lines of both said pattern-select and schedule-select memories the same address signals, designating a tone TN_x, during the existence of one control signal corresponding to a particular time slot TS_y to read out the stored words from such memories,

(j) means responsive to the output from said schedule select memory to make said on/off signal have a corresponding p and q times according to the schedule SCH_u, and

(k) means responsive to the output from said pattern-select memory during each time slot TS_y to cause application of a sample of the pattern PT_z to said bus under the gating control of said on/off signal.

89. In apparatus for signaling any of various ones of a plurality of sounds SD_o -SD_n in any of a plurality of time slots TS_o -TS_n of successive cycles in a PCM multiplex communication system, the combination comprising

(a) an addressable, readable main memory storing, for each of the sounds SD_o -SD_n, in addressable word locations, the successive digital multi-bit samples which represent that sound,

(b) means for producing control signals CT_o -CT_n which exist during and uniquely identify each of the time slots TS_o -TS_n in a cycle,

(c) means for creating, from time to time, paired command signals in which each pair represents (i) a commanded one of the plurality of sounds SD_o -SD_n and (ii) a commanded one of the time slots TS_o -TS_n in which that commanded one sound is to be signaled,

(d) a read/write sound-select memory having a plurality of addressable word locations,

(e) means responsive to the appearance of a pair of command signals for writing the commanded sound signal into said sound select memory at an address corresponding to and determined by the commanded time slot signal,

(f) means for applying said control signals to the address lines of said sound-select memory to read out therefrom during successive time slots the respective commanded sound signals previously stored, and

(g) means responsive to said read-out commanded sound signals to create, only during each time slot when such commanded sound signals exist, address signals representing the location in said main memory of one sample of those samples which correspond to the sound represented by the read-out commanded

sound signals,

(h) means for applying said address signals to said main memory, and

(i) means for changing the address signals so created and so applied, during any given slot, from cycle to cycle, to scan the samples representing the commanded sound for that slot.

90. In apparatus for signaling various ones of a plurality of tones in different desired ones of a plurality of time slots of successive cycles in a PCM multiplex communication system, the combination comprising

(a) an addressable, readable main memory storing, for each of a plurality of tones, successive multi-bit digital samples representing successive magnitudes of the tone sound,

(b) means for producing control signals CT_o -CT_n which respectively exist during and uniquely identify a plurality of time slots in a cycle,

(c) means for creating, from time-to-time, paired command signals which respectively represent (i) a commanded one of a plurality of tones TN_o -TN_n and (ii) a commanded one of the time slots TS_o -TS_n in which te commanded tone is to be signaled,

(d) a read/write tone-select memory having a plurality of addressable word locations,

(e) means responsive to the appearance of a pair of command signals for writing the commanded tone signal into said tone-select memory at an address location represented and determined by the paired commanded time slot signals, said tone select memory having an addressable word location for each of the time slots,

(f) means for applying said control signals during each time slot to the address lines of said tone-select memory to read therefrom during different time slots of each cycle the respective previously stored commanded tone signals for respective ones of the time slots.

(g) means responsive to read out commanded tone signals, during each of said different time slots, to read from said main memory one of the samples there stored for the tone sound called for by said commanded tone signals, and

(h) means for thereafter incrementing or decrementing the address signals applied to said main memory during the respective time slots of said successive cycles, so that the successive samples for a commanded sound are scanned and outputted during the same, commanded time slot of successive cycles.

91. Apparatus for digitally signaling fixed and switchable sounds in a PCM multiplex communication system, comprising in combination

(a) means for producing control signals CT_o -CT_n which exist respectively during and uniquely identify each of successive time slots TS_o -TS_n of repeating cycles,

(b) an addressable, readable main memory storing a pattern of samples for each of a corresponding plurality of sounds SD_o -SD_n, each set of samples representing, as multi-bit digital words, the successive sample magnitudes of a recurring analog wave which corresponds to a desired sound,

(c) means responsive to a first sub-plurality of said control signals CT_o -CT_n to cause read out, from main memory to a common bus, of one sample of respective pre-assigned sounds, with the samples for a given sound being progressively scanned during the same time slot of successive cycles, whereby the respective pre-assigned sounds are transmitted in the time slots corresponding to said first sub-plurality of control signals in every cycle,

(d) a read/write memory having a plurality of addressable word locations,

(e) means responsive to a second sub-plurality of said control signals fed to the address lines of said read/write memory to cause read out of sound ID signals from memory locations respectively corresponding to the values of said control signals during the corresponding time slots,

(f) means for producing, from time-to-time, pairs of command signals with each pair comprising (e) sound command sound ID signals and (ii) time slot command signals equal to one of said second sub-plurality;

and for applying the sound command ID signals to the input data lines, with application of said time slot command signals to the address lines, of said read/write memory, to write the sound command ID signals,

(g) means responsive to the read-out sound ID signals, as produced by said means (e), to cause read out, from main memory to said command bus, during the time slot when said read-out sound ID signals appear, of one sample for the sound identified by such ID signals, with the samples for a given sound being progressively scanned during the same time slot of successive cycles,

whereby any one of the sound may be carried in any one of the channel time slots which correspond to said second sub-plurality of control signals, as determined by the writing of command sound ID signals into locations of said read/write memory at addresses represented by the paired time slot command signals.

92. Apparatus forming and digitally transmitting on an output bus any one of a plurality of tones TN_o -TN_n, where each tone is constituted by one of a plurality of sounds SD_o -SD_n modulated with any one of a plurality of on/off schedules SCH_o -SCH_n, in a PCM time multiplex system, said apparatus comprising in combination

(a) an addressable, readable main memory storing, for each of said sounds SD_o ;

14 SD_n, as multi-bit numerical values, a pattern of successive samples of at least a symmetrical portion of an analog wave representing that sound, each numerical sample having a unique memory address location,

(b) a sound-select memory storing at addressable locations preselected ones of ID words PI_o -PI_n respectively identifying the sounds SD_o -SD_n,

(c) a schedule-select memory storing at addressable locations preselected ones of schedule ID words SCI_o -SCI_n respectively identifying the schedules SCH_o -SCH_n,

the pairing of a sound ID word with a schedule ID word at corresponding address locations in said two select memories designating a particular tone TN_x,

(d) means for applying, during different time slots TS_o -TS_n of repetitive cycles, preselected ones of tone ID signals TI_o -TI_n to the address line of both said sound and schedule select memories, whereby during different time slots different predetermined pairs of ID words PI_x and SCI_x are signaled at the outputs of such memories,

(e) means responsive to the SCI_x word signals existing during any of said time slots to create a gating signal which exists at on and off levels respectively during that slot over intervals of p and q seconds and which form an on/off schedule SCH_x corresponding to the identification word SCI_x,

(f) means responsive to said PI_x word signals existing during any of same time slots to create and apply, to the address inputs of said main memory, signals which cause read out from main memory one sample forming part of the respresentation of the sound SD_x identified by said PI_x word signals, and

(g) means applying or blocking the sample signals so read-out from main memory respectively to or from an output bus when said gating signal contemporaneously is on or off, respectively.

93. The combination set out in claim 92 wherein said means (f) includes means for reading out successive samples of the sound SD_x during the same time slot of successive cycles, with repetitive scanning of all such samples taken one at a time.

94. The combination set out in claim 92 wherein said means (d) includes

(d1) means for selectively changing the tone ID signals applied during different time slots to the address lines of said sound and schedule select memories, thereby to "switch" different desired tones into particular time slots.

95. Apparatus for digitally transmitting different sounds on an output bus in a PCM time multiplex communication system, said apparatus comprising, in combination

(a) an addressable, readable main memory storing, for each of said sounds, in an addressable memory block--as multi-bit numerical values--successive samples of at least a symmetrical portion of an analog wave representing that sound,

(a1) the stored samples for each sound constituting a set,

(a2) the quantities of samples in at least some of said sets being unequal,

(a3) each of said blocks having a quantity of word locations which is equal to or greater than the quantity of samples stored in that block, and all blocks having output lines coupled to a common output bus,

(a4) said sets being stored in their respective blocks such that the last sample of every set is stored at the same, common addressable word location within a block, and with the samples of each set in sequential rollover order,

(b) means for enabling the reading from one preselected block during the same given time slot within every repetitive cycle of time slots,

(c) means for applying to the address line inputs of all blocks sample select signals which represent, during the same time slot of successive cycles, successive sample addresses within the enabled block, to read out onto said bus signals corresponding to successive samples of a selected sound during a selected time slot of successive cycles, the samples of a set thus being read out in a scanned sequence,

(d) means for detecting when the sample address signals represent said common addressable word location, and

(e) means responsive to detection by said means (d) for changing the sample address signals applied by said means (c) during the ensuring cycle to begin a new scan of the samples in the selected block during the selected time slot of later cycles.

96. Apparatus for outputting successive digital samples of a sound in a PCM multiplex system, said apparatus comprising in combination

(a) an addressable, readable memory storing in successive address locations--as multi-bit digitable words--successive samples S_o -S_n representing successive sample magnitudes of at least a symmetrical portion of a cyclic analog wave corresponding to the desired sound,

(b) means for producing character signals which represent the characteristic of the necessary sequences of successive scans of said samples which will recreate the analog wave in PCM form,

(c) means, operative during a given time slot in recurring cycles, for applying to the address lines of said main memory address signals to effect read out of one sample S_j,

(d) means for changing said address signals prior to the next occurrence of the given time slot to represent the address of the next sample to be read-out, so that the samples are scanned seriatim,

(e) means for detecting when said address signals represent the address of the last sample S_n, and

(f) means responsive to detection by said means (e) and controlled by said character signals to form the succeeding value to be given to said address signals for read-out of the next sample at the beginning of a new scan.

97. The combination set out in claim 96 wherein said character signals designate that the samples are to be repeatedly scanned in first-to-last order, and said means (f) includes

(f'"'"') means for making the succeeding value of said address signals represent the address of the said sample.

98. The method set out in claim 96, wherein said character signals designate that the samples are to be scanned alternately in read-up and read-down address order, and said means (f) and (d) include

(f'"'"') means for making the succeeding value of said address signals represent the address of the next-to-last sample S_n-1, and

(d'"'"') means operative in a scan which follows a read-down scan orderfor decrementing said address signals to scan in read-up address order.

99. The combination defined in claim 96 wherein said character signals designate that the last sample is to be repeated after having been read-out once, and said means (f) includes

(f'"'"') means for making the succedding value of said address signals represent the same last sample address, and thereafter prior to the next occurrence of the given time slot forming the next-succeeding value to be given to said address signals to proceed with a new scan.

100. The apparatus defined in claim 96 wherein said characteristic-representing signals designate that the samples are to be read-out with alternately changed signs during successive scans, and said means (f) includes

(f'"'"') means for complementing the sign bit of the sample read-out signals during the ensuing scan of samples.

101. The combination set out in claim 98, further including

(g) means, operative during a scan of the samples in read-up address order, for detecting when said address signals represent the address of the first sample S_o, and

(h) means responsive to detection by said means (g) for making the address signals during the subsequent occurrences of said given time slot progressively increment until they represent the address of the last sample S_n and the last sample is read out.

102. Apparatus for digitally signaling different ones of sound SD_o -SD_n in different time lots TS_o -TS_n of successive cycles in a PCM time multiplex system, said method comprising

(a) an addressable, readable main memory storing in a group of successive addressable word locations--as multi-bit digital words--successive samples S_o -S_n representing the successive sample magnitudes of at least a symmetrical portion of a cyclic analog wave corresponding to the sound to be reproduced,

(b) means for producing control signals CT_o -CT_n which respectively exist during and uniquely identify different time slots within each recurring cycle,

(c) means responsive to each of said control signals to apply address signals to the address lines of said main memory to effect read-out onto a common bus of one sample of a preselected one of said sounds,

(d) means for changing, from cycle-to-cycle, the address signals created during each of said different time slots to successively scan the samples of the sound preselected for that time slot,

some of sounds SD_o -SD_n being represented by stored sample patterns in said main memory which require different scan sequences such for example as (i) first-to-last;

(ii) first -to-last, last-to-first, first-to-last;

(iii) last sample repeat; and

(iv) sample-signs-true, sample-signs-complemented,

(e) an auxiliary readable memory storing, in separate word locations, scan sequence characteristic signals for each of the respective sounds SD_o -SD_n,

(f) means for applying to the address lines of said auxiliary memory, during each of said different time slots, call signals which will effect read-out of the characteristic signals for the particular sound preselected for that time slot, and

(g) means responsive to the characteristic signals read from said auxiliary memory to control the operation of said means (d) and make address signals change to produce scan sequences which conform to the requirememts of the sound preselected for each of said different time slots.

103. Apparatus for digitally signaling an intercept type tone in a PCM multiplex communication system wherein a given time slot appears in each of on-going cycles recurring at a given rate (e.g. every 125 μ

sec.), said apparatus comprising, in combination

(a) an addressable, readable main memory storing in at least two blocks of words at least two patterns P_a and P_b each made up of an equal plurality of samples S_o -S_n which digitally represent numerically the successive magnitudes of at least two respective sounds SD_a and SD_b,

(b) means normally operative during and only within the duration of each occurrence of the given time slot for applying to the address lines of said memory signals which represent the address of sample S_j in the pattern P_a, and in successive cycles C_i, C_i+1, C_i+2. . . changing such signals progressively to read out the samples S_o -S_n in a scanned order S_j, S_j+1, S_j+2. . . , and

(c) means, effective during alternat ones of successive time intervals occurring in succession at a rate substantially lower than said given rate, for modifying the operation of said means (b) so that it acts with reference to the samples of the pattern P_b rather than those of the pattern P_a.

104. Apparatus for digitally signaling an intercept tone in a PCM multiplex communication system, said apparatus comprising in combination

(a) an addressable, readable main memory storing as multi-bit digital words, successive samples for two sounds, the samples for both sounds being equal in quantity and being stored in respective corresponding word locations of adjacent blocks of the memory, the individual words within each block being addressable by a first plurality of lower order bit signals and the two blocks being individually addressable by a 0 or 1 level in a higher order bit signal,

(b) means for producing a periodically recurring time slot signal CT_x,

(c) means for producing lower order bit signals representing an address number for a word within a block,

(c1) means for applying said address number signals to the address lines of both of said memory blocks during each recurrence of said time slot signal,

(c2) means for modifying said address number signals to call for the next word location in a scanning sequence to form the next address number signals to be produced by said means (c) during the ensuing cycle,

(d) means for producing an alternating signal which alternates between a 0 and 1 level with a periodicity greater than that of said time slot signal, and

(e) means for applying said alternating signal to said memory as said higher order address bit to alternately address the adjacent blocks,

whereby the output signals from said memory represent successive samples of a first sound for a first time interval and the successive samples of a second sound for a second time interval, the first and second intervals recurring alternately.

105. Apparatus for turning a gate on or off according to any one of a plurality of schedules during certain ones of a plurality of time slots in successive cycles in a multiplex communication system, said apparatus comprising, in combination

(a) a readable addressable memory storing strings of 0 and 1 bits of data, one string for each of a plurality of schedules SCH_o -SCH_n, each string containing N bits and being characterized by a different combination of n 1'"'"'s in succession following by m 0'"'"'s in succession, where n and m are integers including zero but not exceeding N,

(b) means for reading out from said memory simultaneously on plural output lines one bit of each string, and cyclically scanning the reading through the N bits of the strings at a predetermined rate, and

(c) means for applying the gate, as its control signal, during each occurrence of said certain ones of time slots of every cycle, the signal appearing on a respective preselected one of said output lines.

106. The combination set out in claim 105 further characterized in that said cycles have a duration on the order of 125 μ

sec. and said predetermined rate is on the order of 50 m.s. per bit.

107. The combination set out in claim 105 further characterized in that

(a'"'"') said memory contains N addressable word locations with each word storing one bit of all of said strings and including

(d) a rollover counter driven by clock pulses occurring at a predetermined rate and having N count states per counter cycle, the output lines of the counter being connected to the address lines of said memory.

108. The combination set out in claim 105 further including

(d) a second readable memory storing at different word locations therein different ones of a plurality of schedule ID signals,

(e) means for applying to the address lines of said second memory, during each time slot of every cycle, address signals which correspond to the location of the ID signals representing the particular schedule SCH_u desired to be created in that time slot, and

(f) means responsive to output signals from said second memory during each time slot for selecting and applying to said gate the corresponding one of the output signals from the first-named memory.

109. For use in a PCM multiplex system, apparatus for signaling different ones of a plurality of sounds SD_o -SD_n on a common output bus during different ones of time slots TS_o -TS_n within repeating cycles, each sound corresponding to a different repeating analog wave, said apparatus comprising in combination

(a) an addressable, readable main memory holding in individual multi-word blocks respective patterns PT_n -PT_n each of which is formed by a plurality of successive multi-bit word samples So₁₄ S_n, --the patterns corresponding to the respective sounds,

(b) a read/write memory (RAM) with a plurality of addressable word locations respectively corresponding to said time slots TS_o -TS_n, said RAM being initially loaded with preformed address signals corresponding to the addresses in said main memory at which are a sample of a pattern respectively preselected to be signaled in the different time slots,

(c) means for creating a succession of control signals CT_o -CT_n which respectively exist during and uniquely identify the time slots TS_o-TSn of each cycle,

(d) means for applying said control signals to the address lines of said RAM to cause readout therefrom of the respective preformed address signals, during the respective time slots of any cycle C_i,

(e) means for applying the address signals read from said RAM to the address lines of said main memory to cause readout from the latter to an output bus a sample of the pattern preselected for each of the time slots,

(f) means responsive to the address signals so applied during each given time slot of any cycle C_i for deriving new address signals representing the next sample to be outputted from the pattern preselected for that time slot, and (g) means for writing into said RAM, at the address corresponding to each given time slot, the new address signals created by said means (f),

whereby the samples of a pattern preselected for any given time slot are successively transmitted to the bus during that same time slot in successive cycles.

110. The combination defined by claim 109 further including

(h) means operative on command from time-to-time for writing into said RAM, at an address location corresponding to a desired time slot, the address of the first sample in a commanded pattern PT,_z, whereby the commanded pattern becomes the new preselected pattern for that given slot.