Letter segmenting apparatus for OCR comprising multi-level segmentor operable when binary segmenting fails

• US 4,206,442 A
• Filed: 03/05/1979
• Issued: 06/03/1980
• Est. Priority Date: 07/03/1974
• Status: Expired due to Term

• Current Assignee: Nippon Electric Company Limited (NEC Corporation)
• Original Assignee: Nippon Electric Company Limited (NEC Corporation)
• Inventors: Hoshino, Yukio, Miyazaki, Toshio
• Primary Examiner(s): Boudreau, Leo H.
• Application Number:
  US06/017,668
• Time in Patent Office: 456 Days
• Field of Search: 340/146.3 H, 340/146.3 SG
• US Class Current: 382/178
• CPC Class Codes: G06V 30/10 Character recognition
• CPC Class Codes: G06V 30/15 Cutting or merging image elements, e.g. region growing, watershed or clustering-based techniques

Abstract

A letter segmenting apparatus for the optical character recognition is disclosed. In response to a binary pattern of signals for a letter group, a proportioning circuit predicts possible locations of dividing lines between the letters. A binary signal processor processes the binary pattern to find correct dividing lines near the predicted locations. When this processor fails to find a correct dividing line, a multi-level signal processor finds the correct dividing line near the predicted location.

Claims

1. An apparatus for segmenting a group of substantially sligned letters of substantially common height and width to produce signals representative of dividing lines for said group, comprising:

a binary pattern memory for storing therein a binary pattern of a frame for said letter group;

a multi-level pattern memory for storing therein a multi-level pattern of said frame;

a frame decision circuit responsive to the binary pattern stored in said binary pattern memory for producing signals representative of a width of said frame;

a proportioning circuit responsive to the frame width signals and a reference signal retained thereby for proportioning said frame width to produce signals representative of possible locations of said dividing lines, said reference signal being representative of said common letter width;

a binary signal processor responsive to the possible location signals and the binary pattern stored in said binary pattern memory for successively deciding correct dividing lines in regions of the respective possible locations until the processor fails to decide a correct dividing line to produce, in each instance, signals representative of the correct dividing line and a control signal representative of whether or not the correct dividing line is decided;

a multi-level signal processor responsive to the control signal representative of failure of said binary signal processor of deciding a correct dividing line, the possible location signals for the last-mentioned dividing line, and the multi-level pattern stored in said multi-level pattern memory for deciding the last-mentioned dividing line to produce signals representative of the last-mentioned dividing line; and

a location adjusting circuit successively responsive to the correct dividing line signals produced by at least one of said binary and multi-level signal processors and responsive to the frame width signals for adjusting the possible location signals so as to improve the possible location represented thereby.

2. An apparatus as claimed in claim 1, said multi-level pattern consisting of multi-level signals representative of quantized degrees of a physical quantity at elementary areas in said frame, said elementary areas being arranged along consecutive elementary lines extending transversely of the alignment of said letters, wherein said multi-level signal processor comprisings:

means for designating a predetermined number of the elementary lines in each of the possible location regions, the designated elementary lines being consecutive to one another;

means for integrating the degrees represented by the multi-level signals for each of said designated elementary lines to produce a signal representative of the integrated degrees; and

means for finding the integrated degree signal representative of the minimum integrated degree, to produce said signals produced by the multi-level signal processor.