Method and means for path independent device reservation and reconnection in a multi-CPU and shared device access system

• US 4,207,609 A
• Filed: 05/08/1978
• Issued: 06/10/1980
• Est. Priority Date: 05/08/1978
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Luiz, Fernando A., Sorg, John H. Jr., Snyder, Harlan C.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Heckler, Thomas M.
• Application Number:
  US05/904,050
• Time in Patent Office: 764 Days
• Field of Search: 364/200 MS File, 364/101, 364/117, 179/18 EA, 179/18 ES
• US Class Current: 710/38
• CPC Class Codes: G06F 11/14 Error detection or correction of the data by redundancy in operation G06F11/16 takes precedence
• CPC Class Codes: G06F 11/2005 using redundant communication controllers
• CPC Class Codes: G06F 11/201 between storage system components
• CPC Class Codes: G06F 11/2089 Redundant storage control functionality
• CPC Class Codes: G06F 13/122 where hardware performs an I/O function other than control of data transfer
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405

Abstract

A method and means for path independent reservation and reconnection of devices to CPU'"'"'s operating in a multi-CPU and shared device access system environment. The multi-CPU and shared device access system comprises a plurality of sets of fan out paths (channels), each set coupling a corresponding CPU as a source node; a plurality of input/output devices; and a plurality of control nodes (control units), each node including means for accessing the devices, for selectively intercepting the paths in order to complete a signal path connection to a single destination device. Each control node further includes means (FIG. 2, element 25'"'"') for storing a table of independent path sets of CPU'"'"'s and reserved devices and means (FIGS. 2-5) for managing the connection of CPU'"'"'s to devices such that for any given selection, reservation or reconnection indication, the table is accessed by at least one control node for ascertaining whether the CPU is a member of a set of interfaces to which the device is reserved, if so, an available path is selected. The control nodes thus allocate dynamically dissimilar path sets to devices and CPU'"'"'s on an allegiance basis in order to increase the signal path connection probability by the devices to counterpart CPU'"'"'s involved in the reservation, release, or reconnection of the device and the CPU.

Claims

1. In a system comprising at least a first and second CPU;

shared input/output devices;

at least a first and second set of fan-out paths (channels), each path set coupling a corresponding CPU as a source node; and

at least a first and second control node, each control node including means for accessing the devices and for selectively intercepting predetermined paths from either set in order to complete a signal path connection to a single destination device;

characterized in that

the system further includes;

means for dynamically allocating dissimilar path sets to devices and CPU'"'"'s on an allegiance basis for increasing the signal path connection probability by devices in respect of their counterpart CPU'"'"'s involved in the selection of reserved devices, or reconnection of a device to a counterpart CPU, said allegiance constituting an a priori association among a given CPU and at least one device for the purpose of processing reservations and access requests to the exclusion of other CPU'"'"'s;

said dynamic path allocation means includes at each control node;

memory means for storing a map defining signal path availability among the system elements;

means for ascertaining device availability;

means responsive to device availability status for initiating a reconnection request;

means for accessing the memory means and for ascertaining path availability responsive either to a CPU-originated signal for device connection over an intercepted fan-out path or an available device reconnection request; and

means for broadcasting any reconnection request over available paths between the control node and the CPU having the requisite device allegiance.

7. In a system according to any one of the claims 1, 2, 4, or 6, wherein the device comprises a direct access storage device.

2. In a system comprising at least a first and second CPU;

shared input/output devices;

at least a first and second set of fan-out paths (channels), each path set coupling a corresponding CPU as a source node; and

at least a first and second control node, each control node including means for accessing the devices and for selectively intercepting predetermined paths from either set for completing a signal path connection to a single destination device;

each CPU, path, control node and device having at least one interface operable as a boundary sharable with a connecting system element for the transfer of information;

characterized in that

each control node includes;

memory means for storing a map of the CPU, node, and path connections;

means for modifying the map responsive to allegiance information from at least one CPU (SHID, SNID) communicated to the control node over an intercepted path and for generating and maintaining CPU and device identity and priority of connection information; and

means for completing the signal path connection for any given reservation or reconnection indication respectively from an originating CPU or available device by accessing the map for ascertaining whether the CPU is a member of a set of interfaces to which the device is reserved and then selecting a path, if available.

3. A method for path independent reservation and reconnection of input/output devices by CPU'"'"'s operating in a multi-CPU and shared device access system, the system including multiple control units, each control unit further including multiple channel/control unit interfaces and control unit/device interfaces, each channel/control unit interface communicating with one CPU while each control unit/device interface communicates with a selected one of the devices, the operating system of each CPU being capable of initiating communications with a device by a START I/O instruction, the execution of this instruction thereby causing control to be relinquished to a series of channel command words (CCW'"'"'s), said series of channel command words, in turn, being sent to the control unit over the channel/control unit interface for selecting and accessing the device, said multi-CPU'"'"'s, channels, control units, and devices forming a control and data pathing network, a CPU reserving a device or a device indicating availability for reconnection by respectively communicating a signal over the appropriate interfaces to the intercepting control unit;

characterized in that

the method comprises the steps of;

forming a map of network topology (FIG.

     3) and storing said map at a control unit (FIG. 2, Element 25'"'"') in the network common to at least a pair of CPU'"'"'s connectable over requisite channel/control unit interfaces;

generating and maintaining CPU and device identity and priority of connection information (FIGS. 4 and

     5);

managing the connection of CPU'"'"'s to devices such that for any given reservation or reconnection indication, the map is accessed by at least one control unit for ascertaining the path set to which connection or reconnection is possible; and

selecting an available path if the CPU is a member of the set of interfaces to which the device is reserved.

4. A method of path independent reservation and reconnection of shared access devices by CPU'"'"'s for use in a system of the type comprising at least a first and second CPU;

a first and second plurality of channels, each plurality of channels coupling a corresponding CPU;

a plurality of input/output devices; and

first and second control units terminating at least one channel, each CPU channel, device, and control unit having at least one interface operable as a boundary sharable with a connecting system element for the transfer of information;

said control unit including means for accessing the devices and for switchably interconnecting channel and device interfaces;

said method comprising the steps of;

forming a map of CPU, control unit, and device connectability, and storing said map at a control unit common to at least a pair of CPU'"'"'s and connectable over requisite channels;

selecting a device by an initiating CPU in which the control unit completes a signal path connection to the destination device by switchably interconnecting channel and device interfaces;

disconnecting the channel from the control unit responsive to device access requests from the CPU and recording the device address and CPU allegiance of the accessed device by the control unit, allegiance constituting an a priori association among a given CPU and at least one device to process reservations and accesses to the exclusion of all other CPU'"'"'s;

causing the destination device to access information as requested by the initiating CPU in a disconnected mode from the control unit and the posting of a completion signal upon satisfaction of the access request;

polling of device status by either one or both of the control units; and

raising a reconnection request on those channels terminating in the respective control units which are associated with the device as determined from the previously recorded device address and CPU allegiance.

5. The method according to claim 4 in which the operating system of each CPU initiates communications with a device with a START I/O instruction, the execution of the instruction causing control to be relinquished to a series of channel command words, said channel command words are, in turn, sent to the control unit over the channel/control unit interface for selecting and accessing the device;

responsive to the reconnection request from the control unit the CPU sends a grant signal invoking the control unit and device address in reply; and

utilizing the device address and control unit identity as a pointer to a predetermined channel command word sequence.

6. In a system comprising at least one CPU partitionable into two logical processors;

a first and second channel coupling the CPU;

a plurality of input/output devices;

a first and second control unit terminating the channels, each control unit including means for accessing the devices and for switchably interconnecting device and channel interfaces, each CPU, channel, device, and control unit having at least one interface operable as a boundary sharable with a connecting system element for the transfer of information, wherein the method for path independent reservation and reconnection of shared access devices by the logical processors comprises the steps of;

forming a map of logical processor, control unit, and device connectability and storing said map for access by each control unit;

selecting a device by an initiating logical processor in which an available control unit completes a signal path connection to the destination device by switchably interconnecting channel and device interfaces;

disconnecting the channel from the control unit responsive to device access requests from the logical processor and recording the device identity and logical processor allegiance of the accessed device by the control unit, said allegiance constituting an a priori association among a given CPU and at least one device for processing reservations and accesses to the exclusion of all other CPU'"'"'s;

causing the destination device to access information as requested by the initiating logical processor in a disconnected mode from the control unit and the posting of a completion signal upon satisfaction of the access request;

polling of device status by either one or both of the control units; and

raising a reconnection request on those channels terminating the respective control units which are associated with the device as determined from the previously recorded device identity and logical processor allegiance.