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Cache arrangement for performing simultaneous read/write operations

  • US 4,208,716 A
  • Filed: 12/11/1978
  • Issued: 06/17/1980
  • Est. Priority Date: 12/11/1978
  • Status: Expired due to Term
First Claim
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1. A cache unit for use with a data processing unit for providing fast access to information fetched from a main store coupled to said cache unit in response to commands received from said data processing unit, said cache unit comprising:

  • a buffer store comprising a plurality of word locations energized into a plurality of levels for storing said information;

    a plurality of address switch selection means corresponding in number to said plurality of levels, each said address switch selection means having a number of inputs connected to receive a corresponding number of addresses from a corresponding number of identical address sources and an output;

    a plurality of address register means corresponding in number to said plurality of levels, each said address register means being coupled to a different one of said plurality of address switch selection means and to a different one of said plurality of said levels, each said address register means for storing the address specifying the word location to be accessed during a cache cycle of operation; and

    ,control circuit means coupled to each of said address switch selection means and to one of said address sources for receiving a set of level signals, said control circuit means for generating a plurality of sets of control signals identifying which one of said plurality of said address sources is connected to supply said address to be loaded into each of said address register means, said control circuit means being operative in response to said set of level signals to cause one of said plurality of sets of control signals to condition the address switch selection means designated by said set of level signals to select for loading into said address register means associated therewith an address from said one of said address sources and also to condition the remaining ones of said plurality of address switch selection means to select for loading into the remaining address register means an address from another one of said address sources enabling information to be written into said one level simultaneously with the accessing of information from the remaining levels during said cache cycle of operation.

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