Cache arrangement for performing simultaneous read/write operations
First Claim
1. A cache unit for use with a data processing unit for providing fast access to information fetched from a main store coupled to said cache unit in response to commands received from said data processing unit, said cache unit comprising:
- a buffer store comprising a plurality of word locations energized into a plurality of levels for storing said information;
a plurality of address switch selection means corresponding in number to said plurality of levels, each said address switch selection means having a number of inputs connected to receive a corresponding number of addresses from a corresponding number of identical address sources and an output;
a plurality of address register means corresponding in number to said plurality of levels, each said address register means being coupled to a different one of said plurality of address switch selection means and to a different one of said plurality of said levels, each said address register means for storing the address specifying the word location to be accessed during a cache cycle of operation; and
,control circuit means coupled to each of said address switch selection means and to one of said address sources for receiving a set of level signals, said control circuit means for generating a plurality of sets of control signals identifying which one of said plurality of said address sources is connected to supply said address to be loaded into each of said address register means, said control circuit means being operative in response to said set of level signals to cause one of said plurality of sets of control signals to condition the address switch selection means designated by said set of level signals to select for loading into said address register means associated therewith an address from said one of said address sources and also to condition the remaining ones of said plurality of address switch selection means to select for loading into the remaining address register means an address from another one of said address sources enabling information to be written into said one level simultaneously with the accessing of information from the remaining levels during said cache cycle of operation.
0 Assignments
0 Petitions
Accused Products
Abstract
A cache system includes a storage unit organized into a plurality of levels, each including a number of multiword blocks and a corresponding number of address selection switches and address registers. Each address selection switch has a plurality of different positions connected to receive address signals from a plurality of address sources. A decoder circuit generates output signals for controlling the operation of the address selection switches. In response to previously defined level signals, the decoder circuit conditions a specified one of the number of switches to switch from a first position to a second position. An address specifying the location into which memory data is to be written is clocked into one address register while the address specifying the location from which an instruction is to be fetched is clocked into the remaining address registers. A comparator circuit compares signals indicating the level into which memory data is to be written with signals indicating the level from which a next instruction is to be fetched. The comparator circuit generates signals which cause the delay of instruction access when there is a conflict between writing memory data and accessing instructions.
-
Citations
42 Claims
-
1. A cache unit for use with a data processing unit for providing fast access to information fetched from a main store coupled to said cache unit in response to commands received from said data processing unit, said cache unit comprising:
-
a buffer store comprising a plurality of word locations energized into a plurality of levels for storing said information; a plurality of address switch selection means corresponding in number to said plurality of levels, each said address switch selection means having a number of inputs connected to receive a corresponding number of addresses from a corresponding number of identical address sources and an output; a plurality of address register means corresponding in number to said plurality of levels, each said address register means being coupled to a different one of said plurality of address switch selection means and to a different one of said plurality of said levels, each said address register means for storing the address specifying the word location to be accessed during a cache cycle of operation; and
,control circuit means coupled to each of said address switch selection means and to one of said address sources for receiving a set of level signals, said control circuit means for generating a plurality of sets of control signals identifying which one of said plurality of said address sources is connected to supply said address to be loaded into each of said address register means, said control circuit means being operative in response to said set of level signals to cause one of said plurality of sets of control signals to condition the address switch selection means designated by said set of level signals to select for loading into said address register means associated therewith an address from said one of said address sources and also to condition the remaining ones of said plurality of address switch selection means to select for loading into the remaining address register means an address from another one of said address sources enabling information to be written into said one level simultaneously with the accessing of information from the remaining levels during said cache cycle of operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 35)
-
- 23. A cache unit for use with a data processing unit for providing fast access to data and instructions fetched from a main store coupled to said cache unit in response to commands received from said data processing unit, said cache unit comprising:
-
24. a buffer store comprising a plurality of word locations organized into a plurality of levels for storing said data and instructions;
-
a plurality of multiposition address switch selection means corresponding in number to said plurality of levels, each said address switch selection means having a number of sets of input terminals connected to receive a corresponding number of addresses from a corresponding number of identical address sources, a plurality of output terminals and a plurality of control input terminals; a plurality of address register means corresponding in number to said plurality of levels, each said address register means being coupled to a different one of said address switch selection means plurality of output terminals and to a different one of said plurality of said levels, each said address register means for storing the address specifying the word location to be accessed during a cache cycle; split cycle timing means for generating timing signals for defining first and second halves of said cache cycle; control circuit means coupled to said timing means and to each plurality of control terminals of each said address switch selection means and to one of said plurality of said address sources for receiving a set of level signals, said control circuit means for generating a plurality of sets of control signals for application to said address switch selection means control terminals coded for identifying which address source is connected to supply said address to be loaded into each of said address register means during said first and second halves of said cache cycle, said control circuit means being operative in response to said set of level signals to cause one of said plurality of sets of control signals to condition one of said plurality of address switch selection means designated by said set of level signals to select for loading into said address register means associated therewith an address from said one address source also to condition and the remaining ones of said plurality of address switch selection means to select for loading into the remaining address register means an address from another one of said address sources enabling memory data to be written into said one level simultaneously with the accessing of instructions/operand data from the remaining levels during one of said halves of said cache cycle.
-
- 31. instruction address register means operatively coupled to said data processing unit, to said comparator circuit means and to the same another one of said sets of input terminals of each of said address switch selection means, said address register means including a number of bit positions, a first group of said bit positions for storing an address specifying a next location within said buffer store from which an instruction word is to be accessed and a second group of said bit positions for storing said another set of level signals designating the level from which said instruction word is to be accessed during said first half of said cache cycle in the absence of said conflict condition.
-
33. A cache system for use with a data processing unit for providing fast access to instructions and data fetched from a main store coupled to said cache unit in response to commands received from said data processing unit, said cache unit comprising:
-
a cache store comprising a plurality of word locations organized into a plurality of levels for storing said data and instructions; a plurality of multiposition address switches corresponding in number to said plurality of levels, each said address switch having a number of sets of input terminals connected to receive a corresponding number of addresses from a corresponding number of identical address sources, a plurality of output terminals and a plurality of control input terminals; a plurality of address registers corresponding in number to said plurality of levels, each said address register being coupled to a different one of said plurality of output terminals of said plurality of address switches and to a different one of said plurality of said levels, each said address register for storing the address specifying the word location to be accessed during a cache cycle of operation; split cycle timing means for generating timing signals for defining first and second halves of each cache cycle; comparator circuit means for detecting the presence of a conflict condition between a pair of said address sources, said comparator circuit means having a pair of sets of inputs, one set of inputs being coupled to receive said level signals from said one of said address sources and the other set of inputs being coupled to receive another set of level signals associated with the operation being performed by said another address source, said comparator circuit means being operative to generate an output signal indicative of said conflict condition when the operation of writing memory data received from said main store and the operation of accessing data/instructions involves the same level and said comparator means being coupled to a predetermined one of said address sources for enabling the delay of a predetermined one of said operations until said conflict condition is detected as being no longer present; and
,
-
-
34. control circuit means coupled to said timing means, to said plurality of control input terminals of each of said address switches and to one of said address sources for receiving a set of level signals, said control circuit means for generating a plurality of sets of control signals identifying which address source is connected to supply said address to be loaded into each of said address registers, said control circuit means being operative during a cache cycle of operation in response to said set of level signals to cause one of said plurality of sets of control signals to condition one of said plurality of address switches designated by said set of level signals to select for loading into said address register associated therewith an address from said one address source and also conditioning the remaining ones of said plurality of address switches to select for loading into the remaining address registers an address from another one of said address sources enabling information to be written into said one level simultaneously with the accessing of information from the remaining levels during one of said halves of said cache cycle.
Specification