Adaptive delta modulation system

• US 4,208,740 A
• Filed: 12/20/1978
• Issued: 06/17/1980
• Est. Priority Date: 12/20/1978
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Yin, Huo-Bing, Hallett, Robert J.
• Primary Examiner(s): Griffin, Robert L.
• Assistant Examiner(s): Durigon, Peter
• Application Number:
  US05/971,587
• Time in Patent Office: 545 Days
• Field of Search: 325/38 B, 332/11 D, 179/15 AP, 179/15 AV
• US Class Current: 375/249
• CPC Class Codes: H04J 3/04 Distributors combined with modulators or demodulators pulse distributors in general H03K5/15; pulse counters H03K21/00 - H03K29/06; for telegraphy H04L5/22, H04L13/00 - H04L23/00, H04L25/45; for telephony H04Q11/04

Abstract

An adaptive delta modulation system is disclosed which features an improved digital compandor which may be used with a digital integrating network. The compandor executes a companding algorithm having a nonlinear characteristic to provide a rapid increase in step size to follow the fast rising start or fast decaying end of talkspurts in input signals so as to minimize any slope overload distortions and to provide a small increase or decrease in step size during the smooth portion of the talkspurts in input signals to reduce any granular noise effect. The step size generated by the compandor is directly related to the input signal level, providing a maximum companding range in which good signal-to-noise characteristics are preserved for the soft or low voiced speaker as well as for the loud voiced speaker and providing a fast transient response most suitable for telephone applications. The step size logic of the compandor has a built-in minimum step size circuit which insures that a well behaved idle pattern of alternating ones and zeros will appear at the digital output when the input signal is zero, and which provides a mechanism to rapidly build up the step size when an input signal appears. The step sizes can be integrated with an integrating network to reconstruct the input signal. The compandor may be used in conjunction with a digital integrating network which exhibits, for example, a system function, having either a single pole or a zero and a pair of poles which may be real or complex. The filter constants can be chosen to match any input spectrum to obtain optimum performance. A significantly high signal-to-noise ratio and a wide companding range have been obtained with the disclosed compandor. By providing storage elements in the compandor and in a digital integrating network and storing the calculated intermediate values, a plurality of input for output analog signals can be time division multiplexed and delta modulated with a single delta modulation system.

Claims

1. In a delta modulation system including an analog input connected to a first input of an analog signal compare means whose output in turn is connected to a periodic sampling means generating a delta modulated signal d_i at a sampling frequency which is provided to a system output and to the input of a companding means whose companded signal output α

_i is connected through an integrating network means to a reconstructed analog signal input, wherein said companding means further comprises;

a digital switching circuit for calculating

space="preserve" listing-type="equation">α

.sub.i ={(C-B)α

.sub.i-1 } when d.sub.i ≠

d.sub.i-1,

space="preserve" listing-type="equation">α

.sub.i ={(A+C)α

.sub.i-1 } when d.sub.i =d.sub.i-1, and ##EQU3##

space="preserve" listing-type="equation">when d.sub.i =d.sub.i-1 =. . . =d.sub.o for i>

2

where

A, B, C are positive constants less than unity

A+C >

unity

C-B<

unity, and

α

_i for i=0 is the minimum step size generated by said companding means;

whereby rapid adaptive digital companding of the delta modulation signal fed back via said integrating network to said compare means is achieved.

2. The delta modulation system of claim 1, wherein said companding means further comprises:

a delay means connected between said input of said companding means and a delay node;

an inverted exclusive OR gate having first and second inputs connected to said input of said companding means and said delay node, respectively, for generating an output signal when d_i =d_i-1 ;

a first arithmetic means having a control input connected to said output of said inverted exclusive OR gate and a feedback input connected to said companded signal output, for calculating ##EQU4## a second arithmetic means having a first input connected to the output of said first arithmetic means, a feedback input connected to said companded signal output and an output connected to said compandor output, for calculating the product C α

_i-1, adding it to said calculated value of ρ

_i and outputting the sum as α

_i when d_i =d_i-1 =d_i-2 =d_i-3. . . (alike bits >

     3).

3. The delta modulation system of claim 2, wherein said companding means further comprises:

an exclusive OR gate having first and second inputs connected to said input of said companding means and said delay node, for generating an output signal when d_i ≠

d_i-1 ;

a third arithmetic means having a control input connected to said output of said exclusive OR gate, a feedback input connected to said companded signal output and an output connected to a third input of said second arithmetic means, for calculating the value of the product B α

_i-1 ;

said second arithmetic means calculating the value (C-B) α

_i-1 and outputting that value as α

_i when d_i ≠

d_i-1.

4. The delta modulation system of claim 3, which further comprises a minimum step size circuit having a well behaved idle pattern and a selective build-up in step size.

5. The delta modulation system of claim 3, which further comprises:

a time division analog signal multiplexor connected between a plurality of M analog input signal lines and said first input of said analog signal compare means, having a control input connected to a scan clock, for cyclically connecting each of said M input signal lines to said first input of said compare means under control of said scan clock;

a first storage means connected to said output of said first arithmetic means, having a control input connected to said scan clock, for cyclically storing and accessing stored values of ρ

_i for each of said corresponding M input signal lines, under control of said scan clock;

a second storage means connected to said output of said second arithmetic means, having a control input connected to said scan clock, for cyclically storing and accessing stored values of α

_i for each of said corresponding M input signal lines, under control of said scan clock;

said integrating network means being a digital filter for converting the companded delta modulated signal output from said companding means, corresponding to each of said M input signal lines;

a digital amplitude storage means connected to an output of said filter means, having a control input connected to said scan clock, for cyclically storing and accessing stored values of said digitized reconstructed analog signal output from said filter means for each of said corresponding M input signal lines, under control of said scan clock;

a digital-to-analog converter connected between said digitized amplitude storage means and said reconstructed analog signal input of said analog signal compare means to enable the comparison by said compare means of the analog signal corresponding to that one of said plurality of multiplexor inputs connected to said first input of said compare means;

whereby a plurality of analog input signals may be delta modulated with a minimum amount of hardware.

6. The delta modulation system of claim 5, wherein time division multiplexing of both M-input and M-output analog signals is achieved.