Logic circuit

• US 4,209,715 A
• Filed: 12/09/1977
• Issued: 06/24/1980
• Est. Priority Date: 12/14/1976
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Electric Co., Ltd.
• Original Assignee: Tokyo Shibaura Electric Co., Ltd.
• Inventors: Aoki, Kiyoshi
• Primary Examiner(s): Anagnos, Larry N.
• Application Number:
  US05/859,139
• Time in Patent Office: 928 Days
• Field of Search: 307/203, 307/213, 307/215, 307/220 R, 307/225 R, 307/289, 307/291, 328/39, 357/92
• US Class Current: 327/218
• CPC Class Codes: H03K 19/08 using semiconductor devices H03K19/173 takes precedence; wherein the semiconductor devices are only diode rectifiers H03K19/12
• CPC Class Codes: H03K 3/0372 of the master-slave type
• CPC Class Codes: H03K 3/286 bistable
• CPC Class Codes: H03K 3/288 using additional transistors in the input circuit H03K3/289 takes precedence
• CPC Class Codes: H03K 3/72 with means for varying repetition rate of trains

Abstract

A logic circuit comprises four NAND or NOR gates. The first and second gates are cross-coupled and the third and fourth gates are also cross-coupled. The outputs of the first and second gates are coupled to the inputs of the third and fourth gates respectively. Complementary clock pulses are respectively supplied to the first and second gates and the third and fourth gates, and first and second logic inputs are applied to the inputs of the first and second gates, respectively.

Claims

1. A logic circuit comprising:

first and second integrated-injection logic NAND/NOR gates, each having a plurality of inputs and outputs, said first and second NAND/NOR gates being cross-coupled with respect to first inputs and first outputs thereof, said first NAND/NOR gate having second and third inputs connected to receive a first clock signal and a first logic input signal, respectively, and said second NAND/NOR gate having second and third inputs connected to receive said first clock signal and a second logic input signal, respectively, said first and second NAND/NOR gates having second outputs;

third and fourth integrated-injection logic NAND/NOR gates, each having a plurality of inputs and outputs, said third and fourth NAND/NOR gates being cross-coupled with respect to first inputs and first outputs thereof, said third NAND/NOR gate having a second input connected to receive a second clock signal substantially complementary to said first clock signal and a third input connected to said second output of said first NAND/NOR gate, and said fourth NAND/NOR gate having a second input connected to receive said second clock signal and a third input connected to said second output of said second NAND/NOR gate; and

clock means coupled to said NAND/NOR gates for supplying said first clock signal to said second inputs of said first and second NAND/NOR gates and for supplying said second clock signal to said second inputs of said third and fourth NAND/NOR gates, said clock means including;

a first inverting gate comprised of a multiple-collector output transistor having a base input connected to receive a clock signal, and first, second and third collector outputs, said first and second collector outputs of said multiple-collector output transistor providing one of said first and second clock signals; and

a second inverting gate having an input coupled to said third collector output of said multiple-collector output transistor of said first inverting gate, and first and second outputs providing the other of said first and second clock signals, said second inverting gate being an integrated-injection logic inverting gate.

2. The logic circuit according to claim 1 wherein said first inverting gate is an integrated-injection logic inverting gate.

3. The logic circuit according to claim 1 wherein said multiple-collector output transistor of said first inverting gate has a fourth collector output connected together with said third collector output to said input of said second inverting gate of said clock means.

4. The logic circuit according to claim 3, wherein the combined output current of said third and fourth collector outputs of said multiple-collector output transistor of said first inverting gate is larger than that of each of said first and second collector outputs thereof.

5. The logic circuit according to claim 3 wherein said second inverting gate of said clock means further includes third and fourth outputs connected together with said first and second outputs thereof, respectively.

6. The logic circuit according to claim 1 wherein said first and second NAND/NOR gates each have third outputs, and said third and fourth NAND/NOR gates have second outputs which are coupled to said third outputs of said second and first NAND/NOR gates, respectively.

7. The logic circuit according to claim 6 wherein said third and fourth NAND/NOR gates have third outputs which are coupled to said third inputs of said second and first NAND/NOR gates, respectively.

8. The logic circuit according to claim 1 wherein said third and fourth NAND/NOR gates have second outputs which are coupled to said third inputs of said second and first NAND/NOR gates, respectively.

9. The logic circuit according to claim 1 further comprising cross-coupled fifth and sixth integrated-injection logic NAND/NOR gates connected to outputs of said third and fourth NAND/NOR gates.

10. The logic circuit according to claim 1, further comprising cross-coupled fifth and sixth integrated-injection logic NAND/NOR gates connected between said second outputs of said first and second NAND/NOR gates and said third inputs of said third and fourth NAND/NOR gates.

11. A logic circuit comprising:

first and second integrated-injection logic NAND/NOR gates, each having a plurality of inputs and outputs, said first and second NAND/NOR gates being cross-coupled with respect to first inputs and first outputs thereof, said first and second NAND/NOR gates each having a second input connected to receive a first clock signal, and a third input connected to receive first and second logic input signals, respectively, said first and second NAND/NOR gates each having second and third outputs; and

third and fourth integrated-injection logic NAND/NOR gates, each having a plurality of inputs and outputs, said third and fourth NAND/NOR gates being cross-coupled with respect to first inputs and first outputs thereof, said third and fourth NAND/NOR gates having second inputs connected to said second outputs of said first and second NAND/NOR gates, respectively, third inputs connected to receive a second clock signal substantially complementary to said first clock signal, and second outputs connected to said third outputs of said second and first NAND/NOR gates, respectively.

12. A logic circuit comprising:

first and second integrated-injection logic NAND/NOR gates, each having a plurality of inputs and outputs, said first and second NAND/NOR gates being cross-coupled with respect to first inputs and first outputs thereof, said first and second NAND/NOR gates each having a second input which is connected to receive a first clock signal, said first and second NAND/NOR gates each having third inputs and second and third outputs; and

third and fourth integrated-injection logic NAND/NOR gates, each having a plurality of inputs and outputs said third and fourth NAND/NOR gates being cross-coupled with respect to first inputs and first outputs thereof, said third and fourth NAND/NOR gates having second inputs connected to receive a second clock signal substantially complementary to said first clock signal, third inputs connected to said second outputs of said first and second NAND/NOR gates, respectively, second outputs connected to said third inputs of said second and first NAND/NOR gates, respectively, and third outputs connected to said third outputs of said second and first NAND/NOR gates, respectively.

13. A logic circuit comprising:

a plurality of cascade-connected stages, each stage including;

first and second integrated-injection logic NAND/NOR gates, each having a plurality of inputs and outputs and being cross-coupled with respect to their first inputs and first outputs, second inputs of said first and second NAND/NOR gates being connected to receive a first clock signal; and

third and fourth integrated-injection logic NAND/NOR gates, each having a plurality of inputs and outputs and being cross-coupled with respect to their first inputs and first outputs, said third and fourth NAND/NOR gates having second inputs connected to receive a second clock signal substantially complementary to said first clock signal, third inputs connected to second outputs of said first and second NAND/NOR gates, respectively, and second outputs connected to third inputs of said first and second NAND/NOR gates of an immediately succeeding stage; and

means coupling second outputs of the third and fourth NAND/NOR gates of the final stage to third inputs of second and first NAND/NOR gates of the first stage, respectively.

14. The logic circuit according to claim 13 wherein said first, second, third and fourth NAND/NOR gates have third outputs, said third outputs being connected to said third outputs of said second and first NAND/NOR gates, respectively.

15. A logic circuit comprising:

first and second integrated-injection logic NAND/NOR gates, each having a plurality of inputs and outputs, said first and second NAND/NOR gates being cross-coupled with respect to first inputs and first outputs thereof, said first NAND/NOR gate having second and third inputs connected to receive a first clock signal and a first logic input signal, respectively, and said second NAND/NOR gate having second and third inputs connected to receive said first clock signal and a second logic input signal, respectively, said first and second NAND/NOR gates having second outputs;

third and fourth integrated-injection logic NAND/NOR gates, each having a plurality of inputs and outputs, said third and fourth NAND/NOR gates being cross-coupled with respect to first inputs and first outputs thereof, said third NAND/NOR gate having a second input connected to receive a second clock signal substantially complementary to said first clock signal and a third input connected to said second output of said first NAND/NOR gate, and said fourth NAND/NOR gate having a second input connected to receive said second clock signal and a third input connected to said second output of said second NAND/NOR gate; and

clock means coupled to said NAND/NOR gates for supplying said first clock signal to said second inputs of said first and second NAND/NOR gates and for supplying said second clock signal to said second inputs of said third and fourth NAND/NOR gates, said clock means including;

a first integrated-injection logic inverting gate having an input connected to receive a clock signal, and first and second outputs;

a second integrated-injection logic inverting gate having an input connected to said first output of said first inverting gate, and first and second outputs providing one of said first and second clock signals;

a third integrated-injection logic inverting gate having an input connected to said second output of said first inverting gate, and a first output, and

a fourth integrated-injection logic inverting gate having an input connected to said first output of said third inverting gate, and first and second outputs providing the other of said first and second clock signals, the time for an input potential of said second gate to change from a low level to a high level being longer than that of said third gate.