Signal processing and memory arrangement

• US 4,209,852 A
• Filed: 11/11/1974
• Issued: 06/24/1980
• Est. Priority Date: 11/11/1974
• Status: Expired due to Term

• Current Assignee: Gilbert P. Hyatt
• Original Assignee: Gilbert P. Hyatt
• Inventors: Hyatt, Gilbert P.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US05/522,559
• Time in Patent Office: 2,052 Days
• Field of Search: 340/173 R, 340/173 CA, 340/173 RC, 307/221 C, 307/221 D, 357/24, 328/37, 365/222, 365/45, 365/183
• US Class Current: 365/222
• CPC Class Codes: B60R 16/0373 Voice control in general G10L
• CPC Class Codes: F21V 23/00 Arrangement of electric circuit elements in or on lighting devices characterised by cooling arrangements F21V29/508
• CPC Class Codes: G01S 15/897 using application of holographic techniques
• CPC Class Codes: G01S 15/8977 using special techniques for image reconstruction, e.g. FFT, geometrical transformations, spatial deconvolution, time deconvolution
• CPC Class Codes: G01S 7/52026 Extracting wanted echo signals Doppler systems G01S15/50; Doppler short range imaging systems G01S15/8979
• CPC Class Codes: G02F 1/13318 Circuits comprising a photodetector
• CPC Class Codes: G03F 9/7049 Technique, e.g. interferometric
• CPC Class Codes: G03F 9/7088 Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
• CPC Class Codes: G04G 99/006 Electronic time-pieces using a microcomputer, e.g. for multi-function clocks
• CPC Class Codes: G05B 19/351 the positional error is used to control continuously the servomotor according to its magnitude
• CPC Class Codes: G05B 19/408 characterised by data handling or data format, e.g. reading, buffering or conversion of data
• CPC Class Codes: G05B 19/4083 Adapting programme, configuration
• CPC Class Codes: G05B 19/4086 Coordinate conversions; Other special calculations
• CPC Class Codes: G05B 19/409 characterised by using manual data input [MDI] or by using control panel, e.g. controlling functions with the panel; characterised by control panel details or by setting parameters G05B19/408, G05B19/4093 take precedence
• CPC Class Codes: G05B 19/4093 characterised by part programming, e.g. entry of geometrical information as taken from a technical drawing, combining this with machining and material information to obtain control information, named part programme, for the NC machine
• CPC Class Codes: G05B 19/414 Structure of the control system, e.g. common controller or multiprocessor systems, interface to servo, programmable interface controller
• CPC Class Codes: G05B 19/4142 characterised by the use of a microprocessor G05B19/4141 takes precedence
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G07G 1/12 electronically operated digital data processing aspects G06Q20/00
• CPC Class Codes: G10L 19/00 : Speech or audio signals analysis-synthesis techniques for redundancy reduction, e.g. in vocoders; Coding or decoding of speech or audio signals, using source filter models or psychoacoustic analysis in musical instruments G10H
• CPC Class Codes: G11C 11/565 : using capacitive charge storage elements
• CPC Class Codes: G11C 19/287 : Organisation of a multiplicity of shift registers
• CPC Class Codes: G11C 19/36 : using multistable semiconductor elements
• CPC Class Codes: G11C 27/00 : Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 27/024 : using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: G11C 27/04 : Shift registers
• CPC Class Codes: G11C 7/1039 : using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1042 : using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: Y02P 90/02 : Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

An improved arrangement is provided for processing analog and digital signals, where particular advantages are obtained using charge coupled devices (CCDs). A memory arrangement utilizes a novel refresh circuit to re-establish signal amplitudes which are degraded by a CCD memory. Further, various gating and control circuits are used for loading and unloading the memory. A CCD signal processor and memory arrangement is provided for in an embodiment of an array processing system to exemplify one application of these arrangements.

Claims

1. An analog memory system comprising:

data input means for generating an analog input data signal;

reference input means for generating an analog input reference signal;

means for generating an analog memory input signal in response to the analog input data signal and the analog input reference signal;

memory storing means for storing the analog memory input signal;

memory output means for generating an analog memory output signal in response to the analog signal stored in said memory storing means, said output means including data output means for generating an analog output data signal in response to the analog memory output signal and reference output means for generating an analog output reference signal in response to the analog memory output signal; and

means for processing the analog output data signal in response to the analog output reference signal.

2. The system as set forth in claim 1 above further comprising hybrid memory means for storing digital information in analog signal form.

3. The processing means as set forth in claim 1 above including an implicit servo for processing the output data signal in response to the output reference signal.

4. The processing means as set forth in claim 1 above further comprising a multiplying digital to analog converter for processing the output data signal in response to the output reference signal.

5. The system as set forth in claim 1 above, wherein said storing means includes a charge coupled device for storing a plurality of analog charge signals and shifting means for shifting the stored analog charge signals in response to a sequence of control signals, wherein said system further comprises clock pulse means for generating the sequence of control signals, wherein said analog memory input signal generating means includes means for generating the analog memory input signal having one of a plurality of signal states, and wherein said analog output data signal processing means includes subtraction means for reducing effect of charge leakage.

6. A memory system for storing electrical signals, said memory system comprising:

memory means for storing a plurality of analog signals as stored electrical analog signals;

shifting means for shifting the stored electrical analog signals;

analog data refresh means including means for generation an analog reference signal; and

analog-to-digital converter means for generating digital output signals in response to the stored electrical analog signals.

7. The system as set forth in claim 6 above further comprising means for generating analog input signals to said memory means in response to the digital output signals, said memory means including means for storing the plurality of analog signals in response to the analog input signals.

8. The system as set forth in claim 6 above, wherein said memory means includes charge memory means for storing the analog signals as multiple state electrical analog charge signals having an information content related to the state of the signal.

9. The system as set forth in claim 6 above further comprising an servo for generating an analog output signal in response to the stored analog signals.

10. The system as set forth in claim 6, above further comprising a multiplying digital to analog converter for generating an analog output signal in response to the stored analog signals.

11. A memory system comprising:

memory means for storing information, said memory means including

(a) means for storing the information as a plurality of analog signals and

(b) means for shifting the stored analog signals, wherein the shifting of the stored analog signals degrades the stored analog signals and

means for refreshing the degraded analog signals in response to one of the stored analog signals degraded by the shifting including means for generating an analog reference signal.

39. The system as set forth in claim 11 above;

wherein said memory means includes magnetostrictive means for storing the information in magnetostrictive signal form, wherein said storing means includes means for storing the analog signals as multiple state signals having an information content related to the signal state, and wherein said refreshing means includes scale factor means for reducing amplitude degradation of the stored analog signals and differential means for reducing leakage degradation of the stored analog signals.

12. A memory system comprising:

memory means for storing information, said memory means including storing means for storing a plurality of analog signals and shifting means for shifting the stored analog signals, wherein the shifting of the stored analog signals degrades the stored analog signals;

means for refreshing the degraded analog signals including means for generating an analog reference signal; and

means for generating digital output signals in response to the refreshed analog signals.

23. The system as set forth in claim 12 above, wherein said memory means includes charge storing means for storing the analog signals as multiple state charge signals having an information content related to the state of the multiple charge signals and wherein said refreshing means includes means for reducing amplitude degradation of the degraded analog signals.

24. The system as set forth in claim 12 above further comprising:

information input means for generating an analog information signal;

reference input means for generating an analog reference signal; and

multiplexing means for generating an analog combination signal in response to the analog input signal and the analog reference signal;

wherein said storing means is responsive to the analog combination signal for storing the plurality of analog signals.

13. A memory system comprising:

reference input means for generating an analog reference signal;

information input means for generating an analog information signal;

analog input means for generating an analog input signal in response to the analog reference signal and the analog information signal; and

memory means for storing information, said memory means including

(a) means for storing the information as a plurality of analog signals and

(b) means for shifting the stored analog signals, wherein the shifting of the stored analog signals degrades the stored analog signals; and

means for refreshing the degraded analog signals.

40. The system as set forth in claim 13 above, wherein said memory means includes a magnetostrictive memory for storing the information in magnetostrictive signal form, wherein said storing means includes means for storing the plurality of analog signals as multiple state analog signal having an information content related to the state of the stored signal, and wherein said refreshing means includes scale factor means for reducing amplitude degradation of the degraded analog signals and differential means for reducing leakage degradation of the degraded analog signals.

14. A memory system comprising:

memory means for storing information, said memory means including

(a) storing means for storing a plurality of analog signals and

(b) shifting means for shifting the stored analog signals, wherein the shifting of the stored analog signals degrades the stored analog signals and

means for refreshing the degraded analog signals wherein said refreshing means includes

(a) reference output means for generating an analog reference output signal in response to a stored reference signal and

(b) information output means for refreshing the degraded analog signals in response to the reference output signal.

15. The reference output means as set forth in claim 14 above including a sample and hold circuit for storing the analog reference output signal.

25. The system as set forth in claim 14 above wherein said information output means includes means for increasing amplitude of the degraded analog signals in response to the reference output signal.

26. The system as set forth in claim 14, above further comprising:

information input means for generating a digital input signal and

means for generating a multiple state analog input signal having an information content related to the state of the analog input signal in response to the digital input signal;

wherein said storing means is responsive to the multiple state analog input signal for storing the stored analog signals as multiple state analog signals.

27. The system as set forth in claim 14 above further comprising:

data input means for generating a data input signal and

reference input means for generating a reference input signal;

wherein said storing means includes means for storing the plurality of analog signals in response to the data input signal and the reference input signal.

28. The system as set forth in claim 14 above wherein said system provides for storing digital information in analog signal form, said system further comprising means for generating digital input information and means for generating the stored analog signals in response to the digital input information.

37. The system as set forth in claim 14 above, wherein said memory means includes a charge transfer device for storing the analog signals in charge signal form.

16. A memory system comprising:

data input means for generating a digital input signal;

digital to analog converter means for generating an analog input signal in response to the digital input signal;

reference input means for generating a reference input signal;

means for generating a memory input signal in response to the analog input signal and the reference input signal;

memory means for storing the memory input signal;

output means for generating a memory output signal in response to the signal stored in said memory means, said output means including

(a) data output means for generating an output data signal in response to the memory output signal and

(b) reference output means for generating an output reference signal in response to the memory output signal; and

means for processing the output data signal in response to the output reference signal.

17. The system as set forth in claim 16 above further comprising digital to analog converter means for generating a digital output signal in response to the output data signal.

18. The system as set forth in claim 17 above wherein said digital input signal generating means includes select means for selecting the digital output signal as the digital input signal.

29. The system as set forth in claim 16 above further comprising recirculation means for generating the memory input signal in response to the memory output signal.

30. The system as set forth in claim 16 above further comprising digital output means for generating a digital output signal in response to the memory output signal.

38. The system as set forth in claim 16 above, wherein said memory means includes charge storage means for storing the memory input signal as a multiple state electrical charge signal having an information content related to the state of the multiple level electrical charge signal and wherein said processing means includes a differential circuit for reducing charge leakage degradation of the output data signal in response to subtraction of the output reference signal.

19. A memory system comprising:

information input means for generating an analog information signal;

reference input means for generating an analog reference signal;

storing means for storing the analog information signal generated by said information input means and the analog reference signal generated by said reference input means; and

refreshing means for generating a refreshed analog information signal in response to the stored analog information signal and the stored analog reference signal.

20. The system as set forth in claim 19 above, wherein said information input means includes:

digital input means for generating a digital information signal and

converter means for generating the analog information signal in response to the digital information signal.

21. The system as set forth in claim 19 above further comprising means for generating a comparison signal in response to the stored analog reference signal and the stored analog information signal.

22. The system as set forth in claim 19 above further comprising reference output means for generating a reference output signal in response to the stored analog reference signal;

wherein said refreshing means includes means for reducing degradation of the stored analog information signal in response to the stored analog reference signal.

31. A hybrid memory system for storing digital information in analog signal form, said system comprising;

memory means for storing a plurality of electrical analog signals;

shifting means for shifting the stored electrical analog signals;

converter means for generating electrical digital output signals in response to the stored analog signals;

means for storing a reference signal; and

means for processing the stored analog signals in response to the stored reference signal.

32. A hybrid memory system for storing digital information in analog signal form, said system comprising:

memory means for storing a plurality of electrical analog signals;

shifting means for shifting the stored electrical analog signals;

converter means for generating electrical digital signals in response to the stored analog signals;

means for storing a reference signal in said memory means and

means for refreshing the stored analog signals in response to the stored reference signal.

33. A hybrid memory system for storing digital information in analog signal form, said system comprising:

memory means for storing a plurality of electrical analog signals;

shifting means for shifting the stored electrical analog signals;

converter means for generating electrical digital signals in response to the stored analog signals;

means for generating an analog input signal in response to the digital information;

means for generating an analog reference input signal; and

means for generating the plurality of analog signals to be stored in said memory means in response to the analog input signal and the analog reference input signal.

34. A hybrid memory system storing digital information in analog signal form, said system comprising:

memory means for storing a plurality of electrical analog signals;

shifting means for shifting the stored electrical analog signals;

converter means for generating electrical digital signals in response to the stored analog signals; and

means for storing a reference signal and means for refreshing the stored analog signals in response to the stored reference signal.

35. A memory system comprising:

input means for (selecting one of a plurality of) generating digital input signals

means for generating electrical analog signals in response to the digital input signals;

memory means for storing a plurality of the electrical analog signals,

means for shifting the stored electrical analog signals;

converter means for generating digital output signals in response to the stored electrical analog signals;

means for storing a reference signal and

means for processing the stored analog signals in response to the stored reference signal.

36. A hybrid memory system for storing analog information in response to digital input information, said system comprising:

memory means for storing information, said memory means including

(a) means for storing a plurality of analog signals

(b) means for shifting the stored analog signals, wherein the shifting of the stored analog signals degrades the stored analog signals;

means for refreshing the degraded analog signals;

means for storing a reference signal, wherein said refreshing means includes means for refreshing the degraded analog signals in response to the stored referece signal.