Controller for magnetic disc, recorder, or the like

• US 4,210,959 A
• Filed: 05/10/1978
• Issued: 07/01/1980
• Est. Priority Date: 05/10/1978
• Status: Expired due to Term

• Current Assignee: Apple Computer Incorporated (Apple Inc.)
• Original Assignee: Apple Computer Incorporated (Apple Inc.)
• Inventors: Wozniak, Stephen G.
• Primary Examiner(s): Nusbaum, Mark E.
• Application Number:
  US05/904,420
• Time in Patent Office: 783 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/200, 364/900, 360/69, 360/71, 360/78, 360/135
• US Class Current: 710/74
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0673 Single storage device

Abstract

A controller for interfacing between a digital computer and a magnetic disc recorder, such as a "floppy" disc, or other recorder or memory is disclosed. The controller, which permits accessing of the disc with minimum control by the computer, is realized with relatively few components and is particularly suited for interfacing between a microcomputer and a "minifloppy". Track selection with a computed velocity profile is employed. Synchronization with a soft sectored disc is achieved without additional hardware.

Claims

1. An interfacing means for interfacing between a digital computer and storage device such as a magnetic disc recorder, comprising:

register means having a plurality of parallel input/output lines for coupling to said computer and a serial input/output line for coupling to said storage device, said register means also having a control means having a plurality of register control lines for controlling transfer of data to and from said register means;

latch means having a plurality of latch input lines and a plurality of latch output lines, said latch means for controlling the flow of digital signals between latch input lines and latch output lines in response to a timing signal,

clock means for generating said timing signal,

read-only memory means having an address means with a plurality of address input lines, and a plurality of data output lines, said read-only memory means for receiving input signals on said address input lines and for providing predetermined output signals on said data output lines in response thereto;

a portion of said read-only memory means data output lines being coupled to said register control means via said register control lines for controlling data flow to and from said register, another portion of said read-only memory means data output lines being coupled to said latch means input lines, said latch means output lines being coupled to said addressing means via a portion of said read-only memory means address lines for providing a portion of an address thereto such that some of said output signals from said read-only memory means are employed as next address signals to said read-only memory means in response to said timing signal;

said interfacing means further including means for coupling the addressing means via another portion of said read-only memory means address lines to said computer whereby said computer may communicate with said storage device through said interfacing means.

2. The interfacing means defined by claim 1 including storage means for receiving digital signals from said computer and for providing control signals to said storage device for controlling track selection, said storage means being coupled to said computer and said storage device.

3. The interfacing means defined by claim 2 wherein said means for coupling the addressing means via a portion of said read-only memory address lines to said computer comprises said storage means.

4. The interfacing means defined by claim 3 wherein said input signal to said read-only memory means from said storage means is used to select a reading mode or a recording mode.

5. The interfacing means defined by claim 4 wherein said storage means comprises digital latches.

6. The interfacing means defined by claim 5 wherein said computer has an address bus and a data bus and wherein said ditigal latches are coupled to said address bus of said computer.

7. The interfacing means defined by claim 1 wherein at least one of said output signals from said read-only memory means is coupled to said storage device to provide a signal for a writing mode.

8. The interfacing means defined by claim 7 wherein said register means serially provides a digital signal on said serial input/output line as one of said address inputs to said read-only memory means during said writing mode.

9. The interfacing means defined by claim 8 wherein said output signals from said read-only memory means controls the serial loading of a digital work into said register means during a reading mode.

10. The interfacing means defined by claim 1 wherein said register means receives digital words in parallel form from said computer and serially couples said words to said read-only memory means during a writing mode.

11. The interfacing means of claim 1 wherein said several input/output line of said register means is coupled to said recorder through said latch means and said read-only memory means.

12. An interfacing means for interfacing between a digital computer and storage device such as a magnetic disc recorder, comprising:

register means having a plurality of parallel input/output lines for coupling to said computer and a serial input/output line for coupling to said storage device, said register means also having a control means having a plurality of register control lines for controlling transfer of data to and from said register means;

latch means having a plurality of latch input lines and a plurality of latch output lines, said latch means for controlling the flow of digital signals between latch input lines and latch output lines in response to a timing signal;

clock means for generating said timing signal;

read-only memory means having an address means with a plurality of address input lines, and a plurality of data output lines, said read-only memory means for receiving input signals on said address input lines and for providing predetermined output signals on said data output lines in response thereto;

a portion of said read-only memory means data output lines being coupled to said register control means via said register control lines for controlling data flow to and from said register, another portion of said read-only memory means data output lines being coupled to said latch means input lines, said latch means output lines being coupled to said addressing means via a portion of said read-only memory means address lines for providing a portion of an address thereto such that some of said output signals from said read-only memory means are employed as next address signals to said read-only memory means in response to said timing signal,

said interfacing means further including means for coupling the addressing means via another portion of said read-only memory means address lines to said computer, said read-only memory means being coupled to receive a data signal from said storage device as an address input on one of said address input lines during reading of data, said read-only memory means being coupled to said serial input/output line of said register means to receive a data signal from said register means as an address input on another of said address input lines, and one of said read-only memory data output lines being coupled to said storage device to provide a data signal thereto during recording of data, whereby said computer may communicate with said storage device through said interfacing means.

13. The interfacing means defined by claim 12 wherein said control signal for said latching means comprises a synchronization signal from said computer.

14. The interfacing means defined by claim 12 including storage means coupled to said computer, said read-only memory means and said storage device for receiving signals from said computer for controlling track selection by said storage device and for selecting said recording or reading of data.