Digital computer with overlapped operation utilizing conditional control to minimize time losses

• US 4,210,960 A
• Filed: 09/02/1977
• Issued: 07/01/1980
• Est. Priority Date: 09/02/1977
• Status: Expired due to Term

• Current Assignee: Sperry Corporation
• Original Assignee: Sperry Corporation
• Inventors: Hanson, Merlin L., Borgerson, Barry R., Tjaden, Garold S.
• Primary Examiner(s): Chapnick, Melvin B.
• Application Number:
  US05/830,305
• Time in Patent Office: 1,033 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 712/230
• CPC Class Codes: G06F 9/226 Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format
• CPC Class Codes: G06F 9/265 by address selection on input of storage

Abstract

A computer which is configured to perform its operations in overlapped fashion. During each computer cycle the next instruction is fetched, the function designated by the previous instruction is executed, and values are stored that were computed with respect to the instruction previous to the one being executed. Thus a three-way overlap is effected. To minimize time penalties due to conditional branches and jumps, each instruction word includes two next instruction address fields, two function fields and two deferred action fields. The computer includes decision logic for providing binary decision signals for conditionally selecting one of the fields from each of the next address fields, the function fields and the deferred action fields thereby conditionally fetching the next instruction, conditionally selecting the function to be performed and conditionally storing values during the same cycle in accordance with the decision signals. Thus the computer has the capability of performing conditional branches each cycle, in an unbroken rhythm.

Claims

1. Conditional control apparatus for a digital computer capable of executing a plurality of instructions, said computer operating in computer cycles during which instruction fetching is overlapped with instruction execution without wasting computer cycles in effecting the overlapped operation, comprising

storage means for storing a plurality of instruction words each having first and second next address control fields and first and second function control fields,

fetching means for fetching an instruction word from said storage means during each computer cycle,

decision logic means for providing first and second decision signals in accordance with conditions generated within said computer,

said fetching means being responsive to said first and second next address control fields of an instruction word fetched in a computer cycle previous to the current computer cycle and to said first decision signal for selecting said first or second next address control field in accordance with said first decision signal and fetching, in said current computer cycle, the next instruction word from said storage means in accordance with the next address control field selected by said first decision signal, and

processor means for executing operations designated by said function control fields,

said processor means being responsive to said first and second function control fields of said instruction word fetched in said previous computer cycle and to said second decision signal for selecting said first or second function control field in accordance with said second decision signal and executing, in said current computer cycle, the operation designated by the function control field selected by said second decision signal,

said decision logic means providing said first and second decision signals for use in said current computer cycle in accordance with conditions generated within said computer in response to execution by said computer, in said previous computer cycle, of an instruction word fetched during a computer cycle occurring before said previous computer cycle,

whereby said fetching of said next instruction word is overlapped with said execution of said operation without wasting computer cycles in effecting said overlapped operation.

2. The apparatus of claim 1 in which said computer cycle occurring before said previous computer cycle, said previous computer cycle and said current computer cycle comprise consecutively occurring computer cycles.

3. The apparatus of claim 1 in which

each said instruction word further includes first and second deferred action control fields,

said decision logic means further includes means for providing a third decision signal in accordance with conditions generated within said computer, and

said apparatus further comprises deferred action means responsive to said first and second deferred action control fields of an instruction word fetched in a computer cycle prior to said current computer cycle and to said third decision signal for selecting said first or second deferred action control field in accordance with said third decision signal and performing, in said current computer cycle, the deferred action designated by the deferred action control field selected by said third decision signal,

said decision logic means providing said third decision signal for use in said current computer cycle in accordance with conditions generated within said computer in response to execution by said computer, in said prior computer cycle, of an instruction word fetched during a computer cycle occurring before said prior computer cycle,

thereby overlapping the performance of said deferred action with said fetching of said next instruction word and said execution of said operation without wasting computer cycles in effecting said overlapped operation.

4. The apparatus of claim 3 in which said computer cycle occurring before said prior computer cycle, said prior computer cycle and said current computer cycle comprise consecutively occurring computer cycles.

5. The apparatus of claim 4 in which said prior computer cycle and said previous computer cycle comprise the same computer cycle with respect to each other.

6. The apparatus of claim 1 in which said fetching means includes address multiplexer and latching means responsive to said first and second next address control fields of said instruction word fetched in said previous computer cycle and to said first decision signal for selectively latching said first or second next address control field in accordance with said first decision signal to provide the address for fetching the next instruction word from said storage means.

7. The apparatus of claim 1 in which said processor means includes function multiplexer and latching means responsive to said first and second function control fields of said instruction word fetched in said previous computer cycle and to said second decision signal for selectively latching said first or second function control field in accordance with said second decision signal for controlling said processor means to execute said operation designated by said function control field selected by said second decision signal.

8. The apparatus of claim 1 in which said storage means comprises an addressable control store, said apparatus further comprising,

means for producing a multi-bit modification word indicative of conditions within said computer,

means responsive to one of said first and second next address control fields and said multi-bit modification word for combining said multi-bit modification word with said one of said first and second next address control fields to develop a branch address, and

means for applying said branch address to said addressable control store to address the next instruction word to be fetched,

whereby a branch may be taken to any one of plural addresses in said addressable control store in accordance with conditions within said computer.

9. The apparatus of claim 8 in which said decision logic means includes means for providing a plurality of further decision signals in accordance with conditions generated within said computer, said plurality of further decision signals providing said multi-bit modification word.

10. A microprogrammable CPU for a digital computer capable of performing at least one macro instruction executable by a plurality of micro instructions, said CPU operating in micro cycles during which micro instruction fetching is overlapped with micro instruction execution without wasting micro cycles in effecting the overlapped operation, comprising

control storage means for storing at least one micro routine corresponding to said macro instruction, said routine comprising a plurality of micro instruction words each having first and second next address control fields and first and second function control fields,

fetching means for fetching a micro instruction word from said control storage means during each micro cycle,

decision logic means for providing first and second decision signals in accordance with conditions generated within said CPU,

said fetching means being responsive to said first and second next address control fields of a micro instruction word fetched in a micro cycle previous to the current micro cycle and to said first decision signal for selecting said first or second next address control field in accordance with said first decision signal and fetching, in said current micro cycle, the next micro instruction word from said control storage means in accordance with the next address control field selected by said first decision signal, and

processor means for executing operations designated by said function control fields,

said processor means being responsive to said first and second function control fields of said micro instruction word fetched in said previous micro cycle and to said second decision signal for selecting said first or second function control field in accordance with said second decision signal and executing, in said current micro cycle, the operation designated by the function control field selected by said second decision signal,

said decision logic means providing said first and second decision signals for use in said current micro cycle in accordance with said conditions generated within said CPU in response to execution by said CPU, in said previous micro cycle, of a micro instruction word fetched during a micro occurring before said previous micro cycle,

whereby said fetching of said next micro instruction word is overlapped with said execution of said operation without wasting micro cycles in effecting said overlapped operation.

11. The CPU of claim 10 in which said micro cycle occurring before said previous micro cycle, said previous micro cycle and said current micro cycle comprise consecutively occurring micro cycles.

12. The CPU of claim 10 in which

each said micro instruction word further includes first and second deferred action control fields,

said decision logic means further includes means for providing a third decision signal in accordance with conditions generated within said CPU, and

said CPU further comprises deferred action means response to said first and second deferred action control fields of a micro instruction word fetched in a micro cycle prior to said current micro cycle and to said third decision signal for selecting said first or second deferred action control field in accordance with said third decision signal and performing, in said current micro cycle, the deferred action designated by the deferred action control field selected by said third decision signal,

said decision logic means providing said third decision signal for use in said current micro cycle in accordance with conditions generated within said CPU in response to execution by said CPU, in said prior micro cycle, a micro instruction word fetched during a micro cycle occurring before said prior micro cycle,

thereby overlapping the performance of said deferred action with said fetching of said next micro instruction word and said execution of said operation without wasting micro cycles in effecting said overlapped operation.

13. The CPU of claim 12 in which said micro cycle occurring before said prior micro cycle, said prior micro cycle and said current micro cycle comprise consecutively occurring micro cycles.

14. The CPU of claim 13 in which said prior micro cycle and said previous micro cycle comprise the same micro cycle with respect to each other.

15. The CPU of claim 10 in which said fetching means comprises address multiplexer and latching means responsive to said first and second next address control fields of said micro instruction word fetched in said previous micro cycle and to said first decision signal for selectively latching said first or second next address control field in accordance with said first decision signal to provide the address for fetching said next micro instruction word from said control storage means.

16. The CPU of claim 10 in which said processor means includes function multiplexer and latching means responsive to said first and second function control fields of said micro instruction word fetched in said previous micro cycle and to said second decision signal for selectively latching said first or second function control field in accordance with said second decision signal for controlling said processor means to execute said operation designated by said function control field selected by said second decision signal.

17. The CPU of claim 10 in which

said computer has a repertoire of macro instructions each executable by a plurality of micro instructions, and

said control storage means comprises means for storing a plurality of micro routines corresponding respectively to said macro instructions, each said micro routine comprising a plurality of micro instruction words each having first and second next address control fields and first and second function control fields.

18. The CPU of claim 17 in which said computer includes main memory means for storing macro instruction words corresponding to macro instructions to be performed by said computer, said macro instruction words including an operation code portion in accordance with the macro instruction to be performed.

19. The CPU of claim 18 further including

macro instruction register means for receiving macro instruction words fetched from said main memory means, said macro instruction register means including a section corresponding to said operation code portion, and

control storage addressing means including said fetching means and coupled to said section of said macro instruction register means corresponding to said operation code portion for addressing said control storage means in accordance with said operation code portion of said fetched macro instruction, thereby addressing said micro routine corresponding to said fetched macro instruction.

20. The CPU of claim 19 in which

said micro routines comprise class base routines and instruction routines, each said class base routine corresponding to micro instructions executed in common for a plurality of macro instructions and each said instruction routine corresponding to micro operations performed for a specific macro instruction, and

said control storage addressing means includes means coupled to said section of said macro instruction register means corresponding to said operation code portion for providing a class base vector signal for addressing said control storage means in accordance with the corresponding class base routine and for providing an instruction vector signal for addressing said control storage means in accordance with the corresponding instruction routine.

21. The CPU of claim 20 in which

each said micro instruction word further includes an address control field, and

said control storage addressing means further includes means responsive to said first next address control field and said address control field of said micro instruction word fetched in said previous micro cycle and to said class base vector signal and said instruction vector signal for selectively combining said class base vector signal or said instruction vector signal with said first next address control field in accordance with said address control field of said micro instruction word fetched in said previous micro cycle, thereby providing a vector address signal for addressing said control storage means selectively in accordance with the corresponding class base routine or the corresponding instruction routine, respectively, when said first decision signal selects said first next address control field.

22. The CPU of claim 21 in which said fetching means includes address multiplexer and latching means responsive to said vector address signal, said second next address control field of said micro instruction word fetched in said previous micro cycle and to said first decision signal for selectively latching said vector address signal or said second next address control field in accordance with said first decision signal to provide the address for fetching said next micro instruction word from said control storage means.

23. The CPU of claim 16 in which said processor means comprises

a processor having first and second data inputs, a data output and control inputs comprising function control inputs and an output control input for controlling said data output, and

local memory means coupled to said first data input for storing data and providing data to said first data input,

said function control inputs being coupled to said function multiplexer and latching means for executing said operation selected thereby.

24. The CPU of claim 23 further including

input data bus means coupled to said second input of said processor for providing data thereto, and

output data bus means coupled to said data output of said processor for receiving data therefrom,

said output data bus means being coupled to said local memory means for providing data thereto for storage therein.

25. The CPU of claim 24 in which

each said micro instruction word further includes first and second deferred action control fields,

said decision logic means further includes means for providing a third decision signal in accordance with conditions generated within said CPU, and

said CPU further comprises deferred action means responsive to said first and second deferred action control fields of a micro instruction word fetched in a micro cycle prior to said current micro cycle and to said third decision signal for selecting said first or second deferred action control field in accordance with said third decision signal and performing, in said current micro cycle, the deferred action designated by the deferred action control field selected by said third decision signal,

said decision logic means providing said third decision signal for use in said current micro cycle in accordance with conditions generated within said CPU in response to execution by said CPU, in said prior micro cycle, of a micro instruction word fetched during a micro cycle occurring before said prior micro cycle,

thereby overlapping the performance of said deferred action with said fetching of said next micro instruction word and said execution of said operation without wasting micro cycles in effecting said overlapped operation.

26. The CPU of claim 25 in which

said deferred action means comprises deferred action control memory means for storing a plurality of deferred action control words, the bits thereof controlling respective discrete deferred actions and

said first and second deferred action control fields comprise respective addresses for addressing said deferred action control memory means,

said third decision signal selecting said deferred action control word addressed by the deferred action control field selected by said third decision signal.

27. The CPU of claim 26 in which said deferred action control memory means comprises

first and second deferred action control memories storing the same deferred action control words at the same addresses with respect to each other,

said first and second deferred action control memories being addressed by said first and second deferred action control fields respectively, and

deferred action multiplexer and latching means responsive to the addressed deferred action control word from each of said first and second deferred action control memories and to said third decision signal for latching a selected one of the addressed deferred action control words in accordance with said third decision signal.

28. The CPU of claim 25 in which

each said micro instruction word further includes a processor output control field,

said decision logic means includes means for providing a fourth decision signal in accordance with conditions generated within said CPU, said fourth decision signal being provided for use in said current micro cycle in accordance with conditions generated within said CPU in response to execution by said CPU, in said prior micro cycle, of said micro instruction word fetched during said micro cycle occurring before said prior micro cycle, and

said deferred action means includes processor output control means responsive to said processor output control field of said micro instruction word fetched in said prior micro cycle and to said fourth decision signal for providing a signal to said output control input of said processor for conditionally coupling said data output of said processor to said output data bus means in accordance with said processor output control field and said fourth decision signal, said output control being performed as a deferred action in said current micro cycle.

29. The CPU of claim 25 in which

each said micro instruction word further includes a local memory writing control field,

said decision logic means includes means for providing a fourth decision signal in accordance with conditions generated within said CPU, said fourth decision signal being provided for use in said current micro cycle in accordance with conditions generated within said CPU in response to execution by said CPU, in said prior micro cycle, of said micro instruction word fetched during said micro cycle occuring before said prior micro cycle, and

said deferred action means includes local memory writing control means responsive to said local memory writing control field of said micro instruction word fetched in said prior micro cycle and to said fourth decision signal for conditionally controlling the writing of data into said local memory means from said output data bus means in accordance with said local memory writing control field and said fourth decision signal, said writing of said local memory means being performed as a deferred action in said current micro cycle.

30. The CPU of claim 25 in which said CPU utilizes static control variables in generating said decision signals and in which

each said micro instruction word further includes a static control variable selector field,

said decision logic means includes means for providing a fourth decision signal in accordance with conditions generated within said CPU, said fourth decision signal being provided for use in said current micro cycle in accordance with conditions generated within said CPU in response to execution by said CPU, in said prior micro cycle, of said micro instruction word fetched during said micro cycle occurring before said prior micro cycle, and

said deferred action means includes a plurality of static control variable storage means responsive to said static control variable selector field of said micro instruction word fetched in said prior micro cycle and to said fourth decision signal for storing the state of said fourth decision signal in one of said static control variable storage means selected in accordance with said static control variable selector field, said static control variable storage being performed as a deferred action in said current micro cycle.

31. The CPU of claim 19 in which

said decision logic means includes means for providing at least one further decision signal in accordance with conditions generated within said CPU, said further decision signal being provided for use in said current micro cycle in accordance with conditions generated within said CPU in response to execution by said CPU, in said previous micro cycle, of said micro instruction word fetched during said micro cycle occurring before said previous micro cycle, and

said control storage addressing means includes means responsive to at least one of said first and second next address control fields and said further decision signal for combining said one next address control field with said further decision signal to provide a control storage address for a vector jump when said first decision signal selects said one of said next address control fields.

32. The CPU of claim 10 in which said control storage means comprises an addressable control store, said CPU further comprising,

means for producing a multi-bit modification word indicative of conditions within said computer,

means responsive to one of said first and second next address control fields and said multi-bit modification word for combining said multi-bit modification word with said one of said first and second next address control fields to develop a branch address, and

means for applying said branch address to said addressable control store to address the next micro instruction word to be fetched,

whereby said micro routine may branch to any one of plural addresses in said addressable control store in accordance with conditions within said computer.

33. The CPU of claim 32 in which said decision logic means includes means for providing a plurality of further decision signals in accordance with conditions generated within said computer, said plurality of further decision signals providing said multi-bit modification word.

34. Conditional control apparatus for a digital computer comprising,

storage means for storing instruction words having first and second next address control fields,

means for producing a multi-bit modification word indicative of conditions within said computer,

means responsive to said first next address control field and to said multi-bit modification word for combining said multi-bit modification word with said first next address control field to develop a vector branch address,

decision logic means for providing a decision signal in accordance with conditions generated within said computer, and

fetching means responsive to said vector branch address, to said second next address control field and to said decision signal for selecting said vector branch address or said second next address control field in accordance with said decision signal and fetching the next instruction word from said storage means in accordance with the address selected by said decision signal,

whereby a vector branch may be taken relative to said first next address control field to any one of plural addresses in said storage means in accordance with conditions within said computer.

35. The apparatus of claim 34 in which said decision logic means includes means for providing a plurality of further decision signals in accordance with conditions generated within said computer, said plurality of further decision signals providing said multi-bit modification word.

36. A micro programmable CPU for a computer capable of performing at least one macro instruction executable by a plurality of micro operations, comprising

control storage means for storing at least one micro routine corresponding to said macro instruction, said routine comprising a plurality of micro instruction words each having first and second next address control fields,

means for producing a multi-bit modification word indicative of conditions within said computer,

means responsive to said first next address control field and to said multi-bit modification word for combining said multi-bit modification word with said first next address control field to develop a vector branch address,

decision logic means for providing a decision signal in accordance with conditions generated within said CPU, and

fetching means responsive to said vector branch address, to said second next address control field and to said decision signal for selecting said vector branch address or said second next address control field in accordance with said decision signal and fetching the next micro instruction word from said control storage means in accordance with the address selected by said decision signal,

whereby said micro routine may branch relative to said first next address control field to any one of plural addresses in said control storage means in accordance with conditions within said computer.

37. The CPU of claim 36 in which said decision logic means includes means for providing a plurality of further decision signals in accordance with conditions generated within said computer, said plurality of further decision signals providing said multi-bit modification word.