Voltage comparator provided with capacitively cascade-connected inverting amplifiers

• US 4,211,942 A
• Filed: 07/18/1978
• Issued: 07/08/1980
• Est. Priority Date: 07/18/1977
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
• Inventors: Aoki, Kazuhide, Kawagai, Kenji
• Primary Examiner(s): Anagnos, Larry N.
• Application Number:
  US05/925,801
• Time in Patent Office: 721 Days
• Field of Search: 307/240, 307/243, 307/251, 307/297, 307/304, 307/355, 307/356, 307/DIG. 3
• US Class Current: 327/64
• CPC Class Codes: G01R 19/16557 Logic probes, i.e. circuits indicating logic state (high, low, O); modifications of electronic switches or gates for indicating state of switch H03K17/18
• CPC Class Codes: H03K 5/249 using clock signals
• CPC Class Codes: H03M 1/42 Sequential comparisons in series-connected stages with no change in value of analogue signal

Abstract

A voltage comparator suitable for use in an analog-to-digital converter such as a successive-approximation converter, and provided with capacitively cascade-connected inverter stages to produce an output signal of a logic level 1 or 0 according to the relationship between the magnitudes of two analog input voltage signals to be compared. A first series circuit of an MOS switching transistor and resistive element is connected between the input and output of the respective inverters; a second series circuit of a MOS switching transistor and resistive element is connected between the input of each inverter and circuit ground. The MOS transistors of the first and second series circuits are simultaneously enabled or disabled by a clock pulse; and two input voltage signals to be compared are alternately applied to the first stage coupling capacitor.

Claims

1. A comparator for comparing a first input voltage signal with a second input voltage signal to provide at an output thereof an output signal of a logic level 1 or 0 depending on the relationship between magnitudes of the first and second input voltage signals comprising:

a plurality of capacitively cascade-connected inverting amplifier stages each including an inverter having an input and an output, a first series connection of a first resistive impedance element and a first switching device connected between said input and output of said inverter, a second series connection of a second resistive impedance element and a second switching device connected between said input of said inverter and a reference potential circuit point, and an input-coupling capacitive element connected to said input of said inverter, said first and second switching devices of said first and second series connections being simultaneously enabled or disabled at a predetermined time interval by a clock pulse signal applied thereto; and

input circuit means for alternately coupling the first and second input voltage signals to an input-coupling capacitive element of a first inverting amplifier stage, said input circuit means being arranged to couple the first input voltage signal to said input-coupling capacitive element of said first inverting amplifier stage when said first and second switching devices are enabled, and to couple the second input voltage signal to said input coupling capacitive element of said first inverting amplifier stage when said first and second switching devices are disabled.

2. A comparator for comparing a first input voltage signal with a second input voltage signal to provide at an output an output voltage signal of logic level 1 or 0 depending on the relationship between magnitudes of the first and second volage signals comprising:

a plurality of capacitively cascade-connected inverting amplifier stages each including a MOS inverter having an input and an output, a first series connection of a first resistive impedance element and a first MOS transistor having its source-drain path connected in series with said first resistive impedance element connected between said input and said output of said inverter, a second series connection of a second resistive impedance element and a second MOS transistor having its source-drain path connected in series with said second resistive impedance element connected between said input of said inverter and a reference potential circuit point, and an input coupling capacitive element connected to the input of said MOS inverter;

a first source of the first input voltage signal;

a second source of the second input voltage signal;

a third MOS transistor having its source-drain path connected between said first source and the input coupling capacitive element of a first inverting amplifier stage;

a fourth MOS transistor having its source-drain path connected between said second source and said input coupling capacitive element of said first inverting amplifier stage; and

means for applying clock pulses to gate electrodes of said first through fourth MOS transistors so that said first and second MOS transistors in each of said inverting amplifier stages and said third MOS transistor are enabled and said fourth MOS transistor is disabled during a first time interval, and said fourth MOS transistor is enabled and said first through third MOS transistors are disabled during a second time interval following the first time interval.

3. A comparator according to claim 2 wherein said first through fourth MOS transistors have the same channel type.