Crystal oscillator using a class B complementary MIS amplifier

• US 4,211,985 A
• Filed: 04/26/1978
• Issued: 07/08/1980
• Est. Priority Date: 09/03/1975
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Yamashiro, Osamu
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US05/900,321
• Time in Patent Office: 804 Days
• Field of Search: 331/116 R, 331/114, 331/116 FE, 331/117 FE, 330/263, 330/264, 330/269, 330/277, 58/23
• US Class Current: 331/116.0FE
• CPC Class Codes: G04F 5/06 using piezoelectric resonators
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03F 3/3028 with symmetrical driving of the end stage
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors

Abstract

In oscillators such as those used in electronic watches, low power consumption is quite desirable. To accomplish this, an oscillator is provided including a complementary inverter amplifier circuit comprising a complementary inverter including a p-channel MIS FET connected to a first source potential, an n-channel MIS FET connected to a second source potential, and the gate of the two FETs being applied with a common linear input. Respective load resistors are connected to the drains of the complementary FETs, an output being derived from the interconnection point of the load resistors or from the drains of the FETs. Further, a bias resistor is connected between the gate and the drain of each of the complementary FETs, the input being supplied to the gates of the FETs through respective capacitors. The p-channel FET and n-channel FET are individually biased so that the circuit may serve as a class B push pull amplifier of low power consumption.

Claims

1. An oscillator circuit including an amplifier means using a complementary MIS inverter circuit and a positive feed-back means connected between the input and the output of said amplifier means for feeding back the output signal of said amplifier means to the input thereof and including an inductive element and capacitance elements provided at the input and the output of said amplifier means, the inverter circuit of said amplifier means including a p-channel and n-channel FETs, a first resistance means connected between the drains of said FETs, second resistance means connected between the drain and gate of said p-channel FET, and third resistance means connected between the drain and gate of said n-channel FET, whereby the bias voltage between the gate and the source of each of said p-channel and n-channel FETs is set to a predetermined voltage.

2. The oscillator circuit according to claim 1, in which said p-channel and n-channel FETs have dc bias points different from each other.

3. The oscillator circuit according to claim 2, in which the gates of said p-channel and n-channel FETs are connected in common through respective capacitors.

4. The oscillator circuit according to claim 1, in which the gate of each of said p-channel and n-channel FETs is biased at a dc potential nearly equal to its drain potential.

5. The oscillator circuit according to claim 4, in which the gates of said p-channel and n-channel FETs are connected in common through respective capacitors.

6. The oscillator circuit according to claim 1, in which the bias potential between the gate and the source of each of said p-channel and n-channel FETs is nearly equal to its threshold voltage.

7. The oscillator circuit according to claim 6, in which the gates of said p-channel and n-channel FETs are connected in common through respective capacitors.

8. The oscillator circuit according to claim 1, in which said positive feed-back means comprises a crystal and a first and a second capacitor connected at both ends of said crystal, respectively.

9. An oscillation circuit comprising:

first and second operating potential terminals;

a push-pull amplifier stage comprising input and output terminals, a first p-channel and a first n-channel FET,

a pair of coupling capacitors each connected between said input terminal and the gate of said each FET,

a pair of bias resistors each connected between the gate and the drain of said each FET for biasing the gate at a dc level nearly equal to its drain potential, and

a pair of load resistors each connected between the drain of said each FET and said output terminal;

a positive feedback circuit comprising first and second capacitors having each one end grounded and each other end connected to said input and output terminals of said amplifier stage, respectively, and a crystal coupled therebetween;

a waveform shaping stage for clipping a signal comprising a second p-channel FET and a second n-channel FET, the gates of which are connected to the drains of said first p-channel and n-channel FETs respectively and the drains of which are connected in common; and

an output terminal of said oscillation circuit connected to the commonly connected drains of said second p-channel and n-channel FETs,

the sources of said first and second p-channel FETs being connected to said first operating potential terminal and the sources of said first and second n-channel FETs being connected to said second operating potential terminal.

10. The oscillator circuit according to claim 9, in which the potential difference between the source and the drain of each of said first p-channel and n-channel FETs is set at a potential nearly equal to its threshold voltage.

11. An oscillator comprising in combination:

first and second operating voltage terminals;

first and second field effect transistors of complementary conductivity types, each having a conduction path and a control electrode for controlling the conductivity of said conduction path, said control electrode connected through a capacitor to an input terminal, said conduction paths connected in series between said operating voltage terminals;

first and second load resistors for said first and second transistors, respectively, connected in series between said conduction paths, the connection between said load resistors serving as an output terminal;

first and second bias resistors provided for said first and second transistors, respectively, for controlling the operation points of the input signal at said control electrodes in cooperation with said first and second load resistors, each of said first and second bias resistors being connected between the control electrode and one end of said conduction path, which is on the side connected to said load resistor, in each of said first and second transistors; and

a regenerative feedback path comprising a crystal connected between said output and input terminals.

12. The oscillator according to claim 11, further comprising third and fourth field effect transistors of complementary conductivity types, each having a conduction path and a control electrode for controlling the conductivity of said conduction path, said control electrodes of the third and fourth transistors being connected to the interconnection between said load resistor and the conduction path of the corresponding one of said first and second transistors, said conduction paths of said third and fourth transistors being connected in series between said operating voltage terminals, the connection between the conduction paths of said third and fourth transistors serving as an output terminal of the oscillator.

13. An oscillation circuit comprising:

a push-pull amplifier comprising a series circuit of p-channel and n-channel FETs, the drains of said FETs being connected to each other through load resistive means, the gate of each of said FETs being connected to the drain thereof through bias resistive means so that said bias resistive means causes the bias voltage between the gate and the source thereof to be set at a predetermined voltage in cooperation with said load resistive means, output means coupled to said drains of said FETs for deriving an a.c. output signal, and input means coupled to the gates of said FETs for applying an a.c. input signal; and

positive feed-back means connected between said input means and said output means for feeding back the output signal of said amplifier to said input means of said amplifier.

14. The oscillation circuit according to claim 13, further comprising a succeeding amplifier including a series circuit of p-channel and n-channel FETs, the drains of which are connected to in common while the gate of each of which is connected to the drain of a respective corresponding channel type FET of said push-pull amplifier.

15. In an electronic watch using a crystal-controlled oscillation circuit, said oscillation circuit comprising:

a push-pull amplifier comprising a series circuit of p-channel and n-channel FETs, the drains of said FETs being connected to each other through load resistive means, the gate of each of said FETs being connected to the drain thereof through bias resistive means so that said bias resistive means causes the bias voltage between the gate and the source thereof to be set at a predetermined voltage in cooperation with said load resistive means, output means coupled to said drain of said FETs for deriving an a.c. output signal, and input means coupled to the gates of said FETs for applying an a.c. input signal; and

positive feed-back means connected between said input means and said output means for feeding back the output signal of said amplifier to said input means of said amplifier, said positive feed-back means including first and second capacitors connected at said input and output means respectively, and a crystal coupled therebetween.

16. An oscillator circuit comprising

a first series circuit of first p-channel and n-channel FETs connected between a pair of power source terminals, and

a second series circuit of second p-channel and n-channel FETs connected between said power source terminals,

said first series circuit including resistive connection means for connecting the drain of said first p-channel FET to the drain of said first n-channel FET and bias means for applying to the gate of each of said first p-channel and n-channel FETs from the drain thereof a bias voltage substantially equal to the drain d.c. potential, and

said second series circuit including first connecting means for connecting the drains of said second p-channel and n-channel FETs in common, and second connecting means for connecting the gates of said second p-channel and n-channel FETs to the drains of said first p-channel and n-channel FETs respectively, thereby causing respective bias points of said second p-channel and n-channel FETs to be substantially equal to those of said first p-channel and n-channel FETs, respectively, and

positive feedback means connected between said resistive connection means and the gates of said first p-channel and n-channel FETs.

17. An oscillator circuit according to claim 16, wherein said positive feed-back means includes a crystal and a pair of capacitors.