Computer store mechanism

• US 4,212,058 A
• Filed: 09/20/1977
• Issued: 07/08/1980
• Est. Priority Date: 09/27/1975
• Status: Expired due to Term

• Current Assignee: National Research Development Corporation
• Original Assignee: National Research Development Corporation
• Inventors: Gunawardena, Jaya A.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Bartz, C. T.
• Application Number:
  US05/834,872
• Time in Patent Office: 1,022 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/133
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems

Abstract

In a computer system having two levels of memory, a random access memory is used as a slave store for both code and directly addressed data. Each slave store word includes two slave address fields, one for the slave address of an operand and the other for the slave address of the next instruction. Validation means are provided to determine whether the word at such a slave address has been overwritten since the slave address was recorded.

Claims

1. A computer system comprising:

(a) a central processing unit;

(b) a main store coupled to said central processing unit, said main store being provided for storing a plurality of data/instruction words at a plurality of addresses;

(c) a slave store coupled to said central processing unit and said main store, said slave store being of faster operating speed than said main store and being provided for storing a plurality of words at a plurality of addresses of lesser number than said main store addresses, each said slave store word including a main field for a respective data/instruction word transferred from said main store and a subsidiary field for at least one slave store address corresponding to the address of a further slave store word including a further data/instruction word transferred from said main store serving as a next instruction or operand associated with the first mentioned data/instruction word;

(d) a storage access controller linking said central processing unit, said main store and said slave store, said storage access controller enabling transfer of data/instruction words from the main store to an appropriate address in said slave store without involving said processing unit, enabling entry of the slave store address of the appropriate next instruction or operand into the subsidiary field of each said appropriate slave store address, and enabling discarding of previous words held in said slave store if necessary on a first-in-first-out basis;

(e) a discard address register within said storage access controller for storing the address in said slave store into which the next data/instruction word transferred from said main store is to be inserted by said storage access controller; and

(f) validation means coupled to said slave store and said discard register, said validation means being provided for comparing the content of said subsidiary address field of the first mentioned data/instruction word with the content of said discard address register to determine whether said further data/instruction word at said slave store address has been overwritten by another data/information word from said main store since said slave store address was written into said subsidiary field.

2. A computer system according to claim 1, wherein the capacity of the discard address register is one bit greater than the number of bits of each slave store address, said subsidiary field includes a tag field of one bit and the storage access controller is arranged to copy the most significant bit of the discard address register into the associated tag field when a slave address is written into the subsidiary field of a word in the slave store, the validation means being arranged to compare said tag field with the value, stored at said slave address, of the most significant bit in the discard address register at the time when the information stored in the main field at the slave address recorded in said subsidiary field was entered at said slave address.

3. A computer system according to claim 2, wherein said subsidiary field includes a slave address overflow bit field adapted to store the most significant bit in the discard address register at the time when information is entered in the main field at said slave address.

4. A computer system according to claim 2, including means for resetting said tag field and setting the corresponding subsidiary field to its own slave address when information is written into the main field of said slave address.

5. A computer system according to claim 1, wherein said subsidiary field includes a flag field of one bit and the storage access controller includes means for setting said flag field when a slave address is written into said subsidiary field.

6. A computer system according to claim 1, wherein said subsidiary field includes two slave address fields, one for the slave address of an operand and the other for the slave address of the next instruction.

7. A computer system according to claim 1, wherein the storage access controller incorporates a current instruction slave address register for storing the slave store address of a current instruction word and a current operand slave address register for storing the slave store address of a current operand.

8. A method of accessing information in a computer system having two levels of memory, one level comprising a main store and the other level comprising a slave store of faster operating speed than said main store and having a lesser number of addresses than said main store, each word in said slave store including a main field of the same size as a word of main store and a subsidiary field capable of containing at least one slave store address, there being provided (i) a storage access controller coupled to said main store and said slave store and including a discard address register for storing the address in said slave store into which the next transfer from said main store is to be inserted by said storage access controller, and (ii) validation means coupled to said slave store and said discard address register, the method comprising:

(a) transferring each of a plurality of words from a respective address in said main store to said main field of a respective address in said slave store determined by the discard address register under the control of said storage access controller, at least one of said words being an instruction and at least another of said words being data, previous words held in said slave store being discarded if necessary on a first-in-first-out basis;

(b) entering the slave store address of data required by said instruction into the subsidiary field of the slave store address of said instruction under the control of said storage access controller; and

(c),prior to execution of said instruction, comparing, in said validation means, the content of the subsidiary field of the slave store address of said instruction with the content of said discard address register to determine whether said data required by said instruction has been overwritten by another word from said main store since the slave store address of said data was written into the subsidiary field of the slave store address of said instruction.

9. A method according to claim 8, wherein the capacity of the discard address register is one bit greater than the number of bits of each slave store address and said subsidiary field includes a tag field of one bit, the method incorporating the steps of copying the most significant bit of the discard address register into the associated tag field when a slave address is written into the slave address field of a word in THE slave store, and comparing, in said validation means, said tag field with the value of the most significant bit in the discard address register at the time when the information stored in the main field at the slave address recorded in said subsidiary field was entered at said slave address.

10. A method according to claim 9, further comprising storing, in a slave address overflow bit field, the most significant bit in the discard address register at the time when information is entered in the main field at said slave address.

11. A method according to claim 9, further comprising resetting said tag field and setting the corresponding subsidiary field to its own slave address when information is written into the main field of said slave address.

12. A method according to claim 8, wherein said subsidiary field includes a flag field of one bit, the method incorporating setting said flag field when a slave address is written into the corresponding subsidiary field under the control of the storage access controller.

13. A method according to claim 8, wherein the discard address register is incremented by one each time a word is transferred from the main store to the slave store.