Pseudo-random binary sequence generator

• US 4,213,101 A
• Filed: 06/15/1977
• Issued: 07/15/1980
• Est. Priority Date: 03/12/1975
• Status: Expired due to Term

• Current Assignee: Francis Bourrinet, Gerard Policand, Jacques Trompette
• Original Assignee: Francis Bourrinet, Gerard Policand, Jacques Trompette
• Inventors: Policand, Gerard, Trompette, Jacques, Bourrinet, Francis
• Primary Examiner(s): Anagnos, Larry N.
• Application Number:
  US05/806,838
• Time in Patent Office: 1,126 Days
• Field of Search: 328/59, 331/78, 364/717
• US Class Current: 331/78
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Abstract

Pseudo-random binary sequence generator using a closed loop shift register. According to the invention, the output of the register feeds a switchable inverter which sends out the pseudo-random sequence of the register, alternately inverted and non-inverted, the inverter being switched once per cycle of the register.

Claims

1. A pseudo-random binary sequence generator arrangement with inverter means;

comprising a periodically operated shift register (1) having a counting cycle and feedback logic means receiving predetermined outputs of said shift register and feeding back binary information to said shift register, said shift register having an input responsive to the binary information from said feedback logic means, said feedback logic means being responsive to a logic signal combination of the logic states of at least two stages of said shift register, said inverter means being a switchable inverter (6) having a data input connected to the output (5) of said shift register (1), a control input (8) and an output (7), said inverter delivering to said output the output sequence of said shift register alternately inverted and non-inverted, said inverter being switched over via said control input once per cycle of said register.

2. The sequence generator as defined in claim 1, wherein said control input (8) of the inverter (6) is connected to the output of a bistable element (12), the latter having a "change" input (13) connected to the output of a decoding network (14, 15), said decoding network receiving parallelly the outputs of said register (1) and delivering a change pulse every time said register (1) is in a definite state.

3. The sequence generator as defined in claim 2, wherein said decoding network (14, 15) includes a display register (15) and a coincidence circuit (14), comparing the state of the shift register (1) and of the display register (15) and sending out to said bistable element (12) the change pulse when the state of said shift register (1) coincides with a state as displayed by said display register.