Programmable sequence controller with drum emulation and improved power-down power-up circuitry

• US 4,213,174 A
• Filed: 05/31/1977
• Issued: 07/15/1980
• Est. Priority Date: 05/31/1977
• Status: Expired due to Term

• Current Assignee: Tour Andover Controls, Inc. (Schneider Electric SE)
• Original Assignee: Tour Andover Controls, Inc. (Schneider Electric SE)
• Inventors: Morley, Richard E., Taylor, William A., Bromberg, Michael A.
• Primary Examiner(s): Ruggiero, Joseph F.
• Application Number:
  US05/802,261
• Time in Patent Office: 1,141 Days
• Field of Search: 364/104, 364/107, 364/200, 364/900, 364/100, 364/103, 364/418, 364/550, 364/551, 307/141, 307/141.4, 307/141.8, 165/13, 165/14, 236/44 R, 236/44 C, 236/46 R, 236/46 A, 236/46 C, 236/DIG. 8
• US Class Current: 700/16
• CPC Class Codes: G05B 19/05 Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
• CPC Class Codes: G05B 2219/11101 Verifying ram data correct, validity, reload faulty data with correct data
• CPC Class Codes: G05B 2219/1161 Signal processing, detect or deliver analog signals
• CPC Class Codes: G05B 2219/14089 Display of control states on cards, by leds
• CPC Class Codes: G05B 2219/14116 Safe, emergency shutdown, esd of system
• CPC Class Codes: G05B 2219/14137 Restart, power up of processor, outputs are off, disabled or hold last state
• CPC Class Codes: G05B 2219/15018 Communication, serial data transmission, modem
• CPC Class Codes: G05B 2219/15048 Microprocessor
• CPC Class Codes: G05B 2219/15062 Battery backup
• CPC Class Codes: G05B 2219/15102 Programmer simulates, behaves like a programming drum

Abstract

A programmable sequence controller is disclosed utilizing digital and analog inputs in order to generate digital output driver signals for the control of external systems or devices. The controller emulates mechanical sequence drums so that at any one time each of the simulated drums within the controller executes one of the addressable drum lines programmed within the drum. Each line of each simulated drum can be programmed to specify the energization or deenergization of any output driver as well as the energization or de-energization of any memory bit utilized by the controller in order to provide communication between drums. Each drum may also be programmed to have one or two sets of exit conditions, which if met, cause the controller to effectively rotate the drum to a specified drum line and execute this new drum line during the next scan of the controller. The controller can also sense emergency conditions and cause any or all of the drums to rotate to a specified line regardless of the drum line then being executed by the controller for each of the drums. An improved power-down, power-up circuitry insures an ordered and complete shutdown of the controller if any of a number of conditions exist, including utility AC failure and impending failure of several of the power supply voltages. Handshaking circuitry between the power supply and the remainder of the controller insures that the controller maintains memory validity for all types of shutdown situations, including momentary losses of any supply voltage.

The programmable sequence controller includes a clock-calendar capable of continued operation during periods of extended power outages. The clock-calendar can be utilized in any drum line to form part of the control scheme.

All programming of the simulated drum lines is performed through an interconnected data communication device such as a teletypewriter and utilizes a simple user-oriented language, with monitoring and diagnostic capability to facilitate debugging.

Claims

1. A programmable sequence controller for control of at least one external device or system, the device or system generating ON/OFF inputs and analog voltage inputs to the controller and the controller generating ON/OFF digital output drivers for driving said device or system through solid state switches or other power amplifying devices, if necessary;

said controller comprising;

(A) signal conditioning circuitry for receiving the digital and analog inputs from the external device or system;

(B) a data and addressing bus;

(C) digital input circuitry communicating with the signal conditioning circuitry and the data bus and responsive to the external device or system digital inputs for providing selected digital inputs onto the data and addressing bus;

(D) an analog multiplexer for receiving the analog inputs from the signal conditioning circuitry so as to select a desired analog input;

(E) an analog to digital converter, controller, and comparator interconnected to the data and addressing bus and the analog multiplexer for comparing a selected analog input with a desired value or for converting an analog input into a number representing the analog input magnitude;

(F) a memory, interconnected with the data and addressing bus;

(G) a clock-calendar for generating a number representing time;

(H) digital output driver circuitry, including signal conditioning circuitry, interconnected to said data and addressing bus and to the solid state switches, if present, or to the device or system, for driving said external device or system with desired ON-OFF signals;

(I) means, interconnected to the data and addressing bus, for interconnecting the controller to an external data communications device for user programming, monitoring, and debugging a control program; and

(J) a central processing unit interconnected to said data and addressing bus for communicating with the digital input circuitry, digital output driver circuitry, analog input multiplexer, analog to digital converter, controller and comparator, memory, clock-calendar, and data communications interconnecting means, said central processing unit programmed to accept a user generated control program representing the desired state of said digital output drivers in relationship to the state of selected digital inputs, and values of selected analog inputs, and value of the clock-calendar, said control program comprising a plurality of addressable drum lines defining a simulated sequence drum, each drum line defining selected output drivers as being in the ON or OFF state and said drum line able to specify at least two sets of exit conditions, each set of exit conditions specifying a drum line to be next executed by the controller, the sets of exit conditions specifying at least one of the states of specified digital inputs, specified digital output drivers, specified analog input values, or time represented by the clock-calendar, the central processing unit further programmed to execute one of the drum lines during each scan of the simulated sequence drum, and to examine the sets of exit conditions of the executed drum line so as to next execute a drum line specified by a set of exit conditions if these exit conditions are satisfied;

whereby the controller executes one line of at least two specifiable different lines of said drum if one of the sets of exit conditions for the presently executed line is satisfied and thereby providing for branching capability.

2. A programmable sequence controller as defined in claim 1, wherein said control program can specify the condition of drum lines in at least two simulated sequence drums and wherein said central processing unit comprises means for scanning and executing any one line of each drum on a repetitive sequential basis, and wherein the control program can specify the ON or OFF state of addressable internal memory bits and wherein the set of exit conditions for all the drum lines of all the drums can make reference to the ON or OFF state of any internal memory bit as part of its set of exit conditions, the central processing unit further programmed to execute drum lines specifying the turning ON or OFF of internal memory bits and to examine sets of exit conditions specifying the states of selected internal memory bits regardless of where the states for these internal memory bits were set;

thereby allowing the simulated sequence drums to indirectly reference each other via the internal memory bits.

3. A programmable sequence controller as defined in claim 2, wherein a set of exit conditions may provide for the comparison of two separate analog inputs as part of said set of exit conditions.

4. A programmable sequence controller as defined in claim 2, wherein said memory includes a random access memory which includes data which may be changed including data concerning a desired control program as well as the number generated by the clock-calendar representing time, and wherein said memory further includes a read-only memory for the storage of instructions and data for programming the central processing unit.

5. A programmable sequence controller as defined in claim 4, wherein the controller further comprises:

(K) means, interconnectable to utility AC and interconnected to the signal conditioning circuitry, data and address bus, digital input circuitry, analog multiplexer, analog to digital converter, controller and comparator, memory, clock-calendar, digital output driver circuitry, data communications interconnecting means, and central processing unit for providing direct current electrical power to the controller;

whereby the controller executes one line of at least two specifiable different lines of said drum if one of the sets of exit conditions for the presently executed line is satisfied and thereby providing for branching capability.

6. A programmable sequence controller as defined in claim 5, wherein the means for providing direct current power further comprises a battery backup system interconnected with the random access memory and clock-calendar for providing continuous power to at least a portion of the random access memory and the clock-calendar so as to maintain valid data in said random access memory as well as to maintain operation of the clock-calendar during power outages.

7. A programmable sequence controller as defined in claim 6, wherein the means for providing direct current power further comprises handshaking circuitry for sensing various power or operating characteristics of the controller, for generating a first signal when a sensed characteristic indicates an impending power or operating failure and wherein the controller further incorporates means, interconnected to the generated first signal, for acknowledging said signal'"'"'s generation by generating a second signal interconnected to the handshaking circuitry, said handshaking circuitry having means for receiving the generated second signal so as to insure the generation of at least a third signal, said third signal communicated to the controller, including the central processing unit so as to cause the central processing unit to command an ordered storage of data and to cause the central processing unit and controller to enter a hold or standby state and therefore no active controlling by the controller, said handshaking circuitry de-generating the first signal upon correction of the power or operating failure indicating sensed characteristic, the controller acknowledging means de-generating the second signal in response to the de-generation of the first signal, and the handshaking circuitry having means for de-generating the third signal after a predetermined time delay upon de-generation of the first signal, and thereby allowing the controller to resume normal operation only after the operating failure has been corrected for at least said predetermined time, thereby insuring a quiescent resumption of the controller operation.

8. A programmable sequence controller as defined in claim 7, wherein the power and operating characteristics of the controller that are sensed by the handshaking circuitry include the presence of utility AC power, the presence of direct current electrical power, and the functioning of the central processing unit.

9. A programmable sequence controller as defined in claim 8, wherein said handshaking circuitry comprises:

(A) a first logic gate for generating a fourth signal (true to false UHOH) if any of the sensed power and operating characteristics indicate an impending power or operating failure;

(B) a flip-flop for generating a fifth and sixth signal (U45, pin 4 true, U45, pin 11 false) in response to the generation of said fourth signal;

(C) amplifying means interconnected to said fifth signal for generating said first signal (true to false POWER-DOWN signal) in response to the fifth signal;

(D) a time delay and amplifying circuit for generating the third signals (a true STANDBY signal, a false CPU RESET signal and a false STANDBY signal), in response to the generation of said sixth signal after a first predetermined length of time, said time delay circuitry having means for providing a second longer time delay for de-generating the third signals after de-generation of the sixth signal;

(E) a second logic gate having an input connected to one of the third signals and a second input connected to the fourth signal, the output of the second logic gate connected to an input of said flip-flop for preventing the change of state of said flip-flop after the fourth signal is generated until the third signal is generated, thereby helping to insure that the flip-flop maintains the generation of the fifth and sixth output signals for at least as long as the first time delay generated by the time delay and amplifying circuitry, and

(F) logic means, having a first input interconnected with the second signal and a second input connected to one of the third signals and an output connected to an input of said first logic gate for insuring that the fourth signal maintains its generation, once the remainder of the controller generates the second signal if the third signals have not been generated and even if the power or operating failure has been corrected, until the time delay and amplifying circuitry generates the third signals, at which time said logic means allows the first logic gate to de-generate the fourth signal if the power or operating failure indicating sensed characteristic has been corrected, thereby insuring the entry of a hold or standby state by the controller once an impending power or operating failure has been perceived by the controller through generation of the second signal even if the power or operating failure is extremely short lived or if a statistical glitch occurs in said flip-flop;

whereby the programmable sequence controller enters a hold or standby state whenever a power or operating failure is detected by the first logic gate regardless of the duration of the power or operating failure and whereby the controller only resumes normal operation after the power or operating condition has been corrected for said second predetermined length of time as generated by the time delay and amplifying circuit so as to insure that the direct current electrical power means of the controller have entered a quiescent state prior to resumption of controller activity.

10. A programmable sequence controller as defined in claim 1, wherein said memory includes a random access memory which includes data which may be changed including data concerning a desired control program as well as the number generated by the clock-calendar representing time, and wherein said memory further includes a read-only memory for the storage of instructions and data for programming the central processing unit.

11. A programmable sequence controller as defined in claim 10, wherein the controller further comprises:

(K) means, interconnectable to a source of utility AC, for providing direct current electrical power to the controller, said means including a battery backup system interconnected with the random access memory and clock-calendar for providing continuous power to at least a portion of the random access memory and the clock-calendar so as to maintain valid data in said random access memory as well as to maintain operation of the clock-calendar during power outages.

12. A programmable sequence controller as defined in claim 1, wherein said controller further comprises:

(K) means, interconnectable to a source of electrical power, for providing direct current electrical power to the controller, and further comprises a battery backup system for providing continuous power to at least a portion of the controller and handshaking circuitry for sensing various power or operating characteristics of the controller, for generating a first signal when a sensed characteristic indicates an impending power or operating failure and wherein the controller further incorporates means, interconnected to the generated first signal, for acknowledging said signal'"'"'s generation by generating a second signal interconnected to the handshaking circuitry, said handshaking circuitry having means for receiving the generated second signal so as to insure the generation of at least a third signal, said third signal communicated to the controller, including the central processing unit so as to cause the central processing unit to command an ordered storage of data and to cause the central processing unit and controller to enter a hold or standby state and therefore no active controlling by the controller, said handshaking circuitry de-generating the first signal upon correction of the power or operating failure indicating a sensed characteristic, wherein said controller acknowledging means de-generates said second signal in response to the de-generated first signal, the handshaking circuitry de-generating the third signal after a predetermined time delay in response to the de-generation of the first signal, thereby allowing the controller to resume normal operation only after the operating failure has been corrected for at least said predetermined time and thereby insuring a quiescent resumption of the controller operation.

13. A programmable sequence controller as defined in claim 12, wherein the power and operating characteristics of the controller that are sensed by the handshaking circuitry include the presence of electrical power from the source of electrical power, the presence of direct current electrical power, and the functioning of the central processing unit.

14. A programmable sequence controller as defined in claim 13, wherein said handshaking circuitry comprises:

(A) a first logic gate for generating a fourth signal (true to false UHOH) if any of the sensed power and operating characteristics indicate an impending power or operating failure;

(B) a flip-flop for generating a fifth and sixth signal (U45, pin 4 true, U45, pin 11 false) in response to the generation of said fourth signal;

(C) amplifying means interconnected to said fifth signal for generating said first signal (true to false POWER-DOWN signal) in response to the fifth signal;

(D) a time delay and amplifying circuit for generating the third signals (a true STANDBY signal, a false CPU RESET signal and a false STANDBY signal), in response to the generation of said sixth signal after a first predetermined length of time, said time delay circuitry having means for providing a second longer time delay for de-generating the third signals after de-generation of the sixth signal;

(E) a second logic gate having an input connected to one of the third signals and a second input connected to the fourth signal, the output of the second logic gate connected to an input of said flip-flop for preventing the change of state of said flip-flop after the fourth signal is generated until the third signal is generated, thereby helping to insure that the flip-flop maintains the generation of the fifth and sixth output signals for at least as long as the first time delay generated by the time delay and amplifying circuitry, and

(F) logic means, having a first input interconnected with the second signal and a second input connected to one of the third signals and an output connected to an input of said first logic gate for insuring that the fourth signal maintains its generation, once the remainder of the controller generates the second signal if the third signals have not been generated and even if the power or operating failure has been corrected, until the time delay and amplifying circuitry generates the third signals, at which time said logic means allows the first logic gate to de-energize the fourth signal if the power or operating failure indicating sensed characteristic has been corrected, thereby insuring the entry of a hold of standby state by the controller once an impending power or operating failure has been perceived by the controller through generation of the second signal even if the power or operating failure is extremely short lived or if a statistical glitch occurs in said flip-flop;

whereby the programmable sequence controller enters a hold or standby state whenever a power or operating failure is detected by the first logic gate regardless of the duration of the power or operating failure and whereby the controller only resumes normal operation after the power or operating condition has been connected for said second predetermined length of time as generated by the time delay and amplifying circuit so as to insure that the direct current electrical power means of the controller have entered a quiescent state prior to resumption of controller activity.

15. A programmable sequence controller as defined in claim 1, further comprising indicators for showing the ON or OFF state of the digital outputs from the external device or system interconnected to the signal conditioning circuitry, the ON or OFF state of the digital output driver circuitry, the type of communication between the external data communications device and the controller, and the state of the means for providing direct current electrical power to the controller.

16. A programmable sequence controller as defined in claim 1, wherein the central processing unit incorporates a microprocessor.

17. A programmable sequence controller as defined in claim 1, wherein the external data communications means further comprises means for communicating between the programmable sequence controller and other programmable sequence controllers or data processing devices.

18. A programmable sequence controller as defined in claim 1, wherein the external device or system is an energy related device or energy control system and wherein the central processing unit is further programmed to accept diagnostic commands user generated by the external data communications device in order to facilitate monitoring and debugging the control program.

19. A programmable sequence controller as defined in claim 18, wherein the diagnostic commands include maintaining the output drivers at designated states while providing for the operation and monitoring of the control program as executed by the controller with the generated states for the driver circuitry disconnected from the external device or system, thereby allowing the user to monitor the execution of a control program without the control program actually controlling the external device or system.

20. A programmable sequence controller as defined in claim 19, wherein the diagnostic commands further include the altering of a selected analog value, the advancing of a drum line, the clearing of a digital input, the disabling of an analog input, the disabling of a selected output driver, the disabling of a selected digital input, the enabling of a selected analog input, the enabling of a selected output driver, the enabling of a selected digital input, the enabling of all digital inputs, analog inputs, and output drivers, the removal of a previously programmed drum line, the rotation of the simulated drum to another drum line, the resetting of the simulated drum to line zero, and the setting of a selected digital input to a specified state.

21. A programmable sequence controller as defined in claim 18, wherein the central processing unit is further programmed to generate error messages communicable to the user via the external data communications device so as to inform the user of any one of a number of errors in the control program.

22. A programmable sequence controller as defined in claim 18, wherein the central processing unit is further programmed to accept print or punch commands user generated by the external data communications device and to generate signals to the data communications device in response thereto, to print or punch information concerning the control program or state of the digital inputs and outputs or values of the analog inputs or time, and thereby facilitate programming and debugging the control program as well as to generate a readout of the control program or portion thereof.

23. A programmable sequence controller as defined in claim 22, wherein said print or punch commands include the printing of a selected analog input, the printing of a selected output driver, the printing of a selected digital input, the printing of a selected simulated drum line, the printing of the entire simulated sequence drum, the printing of the current drum line position, the punching of the entire control program, and the printing of the time as represented by the clock-calendar.

24. A programmable sequence controller as defined in claim 1, wherein the control program can specify the condition of dedicated emergency drum lines in a dedicated emergency simulated sequence drum, the emergency line specifying an emergency set of exit conditions and a specified drum line of the other simulated sequence drum to be next executed by the central processing unit regardless of the drum line of said simulated sequence drum that formerly was executed by the central processing unit and to thereby cause a particular drum line to be executed in response to an emergency condition, the central processing unit comprising means for examining the emergency exit lines of the simulated emergency sequence drum and to cause the other simulated sequence drum to execute the line specified by the emergency drum line if the emergency set of exit conditions is satisfied.

25. A programmable sequence controller for control of at least one external device or system, the device or system generating ON/OFF digital inputs and analog inputs to the controller and the controller generating ON/OFF digital type output drivers for driving said device or system through solid state switches or other power amplifying devices, if necessary, said controller comprising:

(A) a data and address bus;

(B) digital input circuitry for receiving the digital outputs of the external device or system, including buffer circuitry, interconnected with the data and address bus for providing selected digital data onto the data and address bus;

(C) an analog multiplexer for receiving the analog inputs of the external device or system so as to select a desired analog input;

(D) an analog to digital converter, controller, and comparator circuit interconnected to the data and addressing bus and the analog multiplexer for comparing a selected analog input with a desired value or for converting an analog input into a number representing an analog input magnitude;

(E) a memory, interconnected with the data and addressing bus;

(F) digital output driver circuitry, including signal conditioning circuitry, interconnected to the data and addressing bus and to the solid state switches, if present, or to the device or system, for driving said external device or system with desired ON/OFF signals; and

(G) a central processing unit interconnected to the data and addressing bus for communicating with the digital input circuitry, digital output driver circuitry, analog input multiplexer, analog to digital converter, controller and comparator, and memory, said central processing unit having means for generating addressable internal memory bits and programmed to execute a control program representing the desired state of said digital output drivers in relationship to the state of selected digital inputs and addressable internal memory bits, and the values of selected analog inputs, said control program comprising at least two simulated sequence drums, each drum comprising a plurality of addressable drum lines, each drum line defining selected output drivers as being in the ON or OFF state as well as selected internal memory bits as being in the ON or OFF state, and said drum line able to specify a set of exit conditions, each set of exit conditions specifying a drum line to be next executed by the controller, the sets of exit conditions specifying the states of specified digital inputs, specified digital output drivers, specified internal memory bits, or specified analog input values, the central processing unit further programmed to execute one of the drum lines for each simulated sequence drum during each scan of the simulated sequence drums and further programmed so as to allow drum lines of any particular simulated sequence drum to be able to reference other drum lines in other simulated sequence drums only via the state of selected internal memory bits, and the central processing unit further programmed to examine the set of exit conditions for the presently executed drum line of each simulated drum so as to next execute a drum line specified by the set of exit conditions if these exit conditions are satisfied;

whereby the controller executes a different line of any simulated sequence drum if the exit condition for the presently executed line for that sequence drum is satisified and whereby simulated sequence drums may indirectly reference each other via the internal memory bits.

26. A programmable sequence controller as defined in claim 25, wherein the control program may specify a set of exit conditions so as to provide for the comparison of two separate analog inputs as part of a set of exit conditions.

27. A programmable sequence controller as defined in claim 25, further comprising a clock-calendar for generating a number representing time, wherein said number may be utilized in the control program for specifying at least a portion of a set of exit conditions for a drum line based upon elapsed time or absolute calendar time, and wherein the central processing unit is further programmed to utilize the number generated by the clock-calendar to represent a desired elapsed time or absolute calendar time.

28. A programmable sequence controller as defined in claim 27, wherein the controller further comprises means interconnectable to a source of utility power, for providing direct current electrical power to the controller, said means further comprising a battery backup system for providing continuous power to at least a portion of the memory and the clock-calendar so as to maintain the operation of the clock-calendar during power outages.

29. A programmable sequence controller as defined in claim 25, further comprising means, interconnected to the data and addressing bus, for interconnecting the controller to an external data communications device for user programming, monitoring, and debugging the control program.

30. A programmable sequence controller as defined in claim 29, further comprising indicators for showing the ON or OFF state of digital outputs from the external device or system interconnected to the digital input circuitry, the ON or OFF state of the digital output driver circuitry, and the type of communication between the external data communications device and the controller.

31. A programmable sequence controller as defined in claim 30, wherein the central processing unit incorporates a microprocessor.

32. A programmable sequence controller as defined in claim 29, wherein the central processing unit is further programmed to accept diagnostic commands user generated by the external data communications device in order to facilitate monitoring and debugging the control program.

33. A programmable sequence controller as defined in claim 32, wherein the diagnostic commands include disabling a specified internal memory bit, enabling a specified internal memory bit, and setting a specified internal memory bit to a specified state.

34. A programmable sequence controller as defined in claim 33, wherein the diagnostic commands further include maintaining the output drivers at designated states while providing for the operation and monitoring of the control program as executed by the controller with the generated states for the driver circuitry disconnected from the external device or system, thereby allowing the user to monitor the execution of a control program without the control program actually controlling the external device or system.

35. A programmable sequence controller as defined in claim 32, wherein the central processing unit is further programed to generate error messages communicable to the user via the external communications device so as to inform the user of any one of a number of errors in the control program.

36. A programmable sequence controller as defined in claim 35, wherein the central processing unit is further programmed to cause the external data communications device to print or punch information concerning the control program stored within the controller as well as the states of the digital inputs, digital output drivers, and internal memory bits, and the values of the analog inputs and thereby facilitate programming and debugging of the control program as well as to generate a readout of the entire control program or portion thereof.

37. A programmable sequence controller as defined in claim 25, wherein the controller further comprises means, interconnectable to a source of electrical power, for providing direct current electrical power to the controller, said means further comprising a battery backup system for providing continuous power to at least a portion of the controller and handshaking circuitry for sensing various power or operating characteristics of the controller, for generating a first signal when a sensed characteristic indicates an impending power or operating failure and wherein the controller further incorporates means, interconnected to the generated first signal, for acknowledging said signal'"'"'s generation by generating a second signal interconnected to the handshaking circuitry, said handshaking circuitry having means for receiving the generated second signal so as to insure the generation of at least a third signal, said third signal communicated to the controller, including the central processing unit so as to cause the central processing unit to command an ordered storage of data and to cause the central processing unit and controller to enter a hold or standby state and therefore no active controlling by the controller, said handshaking circuitry de-generating the first signal upon correction of the power or operating failure indicating sensed characteristic, wherein said controller acknowledging means de-generates the second signal in response to the de-generated first signal, the handshaking circuitry having means for de-generating the third signal after a predetermined time delay in response to the de-generation of the first signal, thereby allowing the controller to resume normal operation only after the operating failure has been corrected for at least said predetermined length of time and thereby insuring a quiescent resumption of the controller operation.

38. A programmable sequence controller as defined in claim 25, wherein the control program can also represent at least one emergency simulated drum line of a dedicated emergency sequence drum, wherein each emergency drum line can specify a set of emergency exit conditions and a specified drum line in each of the other simulated sequence drums to be next executed by the controller regardless of the drum lines previously executed by the controller for these other simulated sequence drums if the set of emergency exit conditions is satisfied, the central processing unit further programmed to examine the emergency drum lines during each scan of the simulated sequence drums and to cause the specified drum lines for the other simulated sequence drums to next be executed if the emergency exit condition is satisified.

39. A programmable sequence controller for control of at least one external device or system, the device or system generating ON/OFF digital inputs and analog inputs to the controller and the controller generating ON/OFF digital output drivers for driving said device or system, said controller comprising:

(A) a data and address bus;

(B) digital input circuitry for receiving the digital inputs of the external device or system, including buffer circuitry, interconnected with the data and address bus for providing selected digital data onto the data and address bus;

(C) an analog multiplexer for receiving the analog inputs of the external device or system so as to select a desired analog input;

(D) an analog to digital converter, controller, and comparator circuit interconnected to the data and addressing bus and the analog multiplexer for comparing a selected analog input with a desired value or for converting an analog input into a number representing an analog input magnitude;

(E) a memory, interconnected with the data and addressing bus;

(F) digital output driver circuitry, including signal conditioning circuitry, interconnected to the data and addressing bus and communicating with the external device or system, for driving said external device or system with desired ON/OFF signals; and

(G) a central processing unit interconnected to the data and addressing bus for communicating with the digital input circuitry, digital output driver circuitry, analog input multiplexer, analog to digital converter, controller and comparator, and memory, said central processing unit programmed to execute a control program representing the desired state of said digital output drivers in relationship to the state of selected digital inputs and values of selected analog inputs, said control program representing the desired state of said digital output drivers in relationship to the state of selected digital inputs and analog input values, said control program comprising a plurality of addressable drum lines defining a simulated sequence drum, each drum line defining selected output drivers as being in the ON or OFF state and said drum line able to specify at least two sets of exit conditions, each set of exit conditions specifying a drum line to be next executed by the controller, the sets of exit conditions specifying the states of specified digital inputs, specified digital output drivers, or specified analog input values, the central processing unit further programmed to execute one of the drum lines during each scan of the simulated sequence drum, and to examine the sets of exit conditions of the executed drum line so as to execute a drum line specified by a set of exit conditions if these exit conditions are satisified;

whereby the controller executes one line of at least two specifiable different lines of said drum if one of the sets of exit conditions of the presently executed line is satisfied and thereby providing for branching capability.

40. A programmable sequence controller as defined in claim 39, wherein said central processing unit is further programmed to examine each set of exit conditions for the preently executed drum line in sequence, and to terminate examination of all remaining sets of exit conditions of the presently executed line if the presently examined set of exit conditions is satisified.

41. A programmable sequence controller as defined in claim 40, wherein each drum line can specify up to two sets of exit conditions.

42. A programmable sequence controller as defined in claim 39, further comprising:

(H) a clock-calendar for generating a number representing time;

(I) means, interconnected to the data and address bus for interconnecting the controller to an external data communications device for user programming, monitoring, and de-bugging the control program and for allowing interconnection of the controller with other programmable sequence controllers or data processing devices so that these controllers and data processing devices can communicate with each other;

(J) means, interconnectable to a source of electrical power, for providing direct current electrical power to the controller; and

(K) indicators, for showing the ON or OFF state of digital outputs from the external device or system interconnected to the digital input circuitry, the ON or OFF state of the digital output driver circuitry, and the type of communication between the external data communications device and the controller, and the state of the means for providing electrical power to the controller;

wherein the control program can specify the condition of drum lines in at least two simulated sequence drums and wherein the central processing unit comprises means for scanning and executing any one line of each drum on a repetitive sequential basis, and wherein the control program can specify the ON or OFF state of addressable internal memory bits and wherein the set of exit conditions for all the drum lines of all the drums can make reference to the ON or OFF state of any internal memory bit, the central processing unit further programmed to execute drum lines specifying the turning ON or OFF of internal memory bits and to examine sets of exit conditions specifying the states of selected internal memory bits regardless of where the states for these internal memory bits were set, thereby allowing the simulated sequence drums to indirectly reference each other via the internal memory bits; and

wherein the means for providing direct current power further comprises a battery backup system for providing continuous power to at least a portion of the memory and the clock-calendar so as to maintain valid data in at least a portion of the memory as well as to maintain operation of the clock-calendar during power outages and further wherein said means for providing direct current power further comprises handshaking circuitry for sensing various power or operating characteristics of the controller, for generating a first signal when a sensed characteristic indicates an impending power or operating failure and wherein the controller further incorporates means, interconnected to the generated first signal, for acknowledging said signal'"'"'s generation by generating a second signal interconnected to the handshaking circuitry, said handshaking circuitry having means for receiving the generated second signal so as to insure the generation of at least a third signal, the third signal communicated to the controller, including the central processing unit so as to cause the central processing unit to command an ordered storage of data and to cause the central processing unit and controller to enter a hold or standby state and therefore no active controlling by the controller, said handshaking circuitry de-generating the first signal upon correction of the power or operating failure indicating sensed characteristics, wherein said controller acknowledges means de-generates said second signal in response to the de-generated first signal, the handshaking circuitry de-generating the third signal after a predetermined time delay in response to the de-generation of the first signal, thereby allowing the controller to resume normal operation only after the operating failure has been corrected for at least said predetermined time and thereby insuring a quiescent resumption of the controller operation.

43. A programmable sequence controller as defined in claim 42, wherein said memory includes a random access memory which includes data which may be changed including data concerning the desired control program as well as the number generated by the clock-calendar representing time, and wherein the memory further comprises a read-only memory for the storage of instructions and data for programming the central processing unit;

and wherein the power and operating characteristics of the controller that are sensed by the handshaking circuitry include the presence of utility AC power, the presence of direct current electrical power, and the functioning of the central processing unit, and wherein the central processing unit comprises a microprocessor.

44. A programmable sequence controller for the control of at least one external device or system, the device or system generating inputs to the controller and the controller generating output driver signals for driving said device or system, said controller comprising:

(A) input circuitry communicating with the inputs from the external device or system, and responsive thereto, for generating signals of selected inputs;

(B) output driver circuitry, interconnected to the device or system for generating output driver signals; and

(C) a central processing unit communicating with the input circuitry and output driver circuitry, said central processing unit programmed to execute a control program representing the desired state of the output driver signals in relationship to the state of selected inputs from the external device or system, generated by the input circuitry, said control program comprising a plurality of addressable drum lines defining a simulated sequence drum, each drum line defining selected output driver signals as being as selected states and said drum line able to specify at least two sets of exit conditions, each set of exit conditions specifying a drum line to be next executed by the controller, the sets of exit conditions specifying the states of specified inputs from the external device or system and specified output driver signals, the central processing unit further programmed to execute one of the drum lines during scan of the simulated sequence drum, and to examine the sets of exit conditions of the executed drum line so as to next execute a drum line specified by a set of exit conditions if these exit conditions are satisfied;

whereby the controller executes one line of at least two specifiable different lines of said drum if one of the sets of exit conditions for the presently executed line is satisfied and thereby providing for branching capability.

45. A programmable sequence as defined in claim 44, wherein the central processing unit is further programmed to examine the sets of exit conditions for a presently executed drum line in a sequential fashion and to terminate the examination of the sets of exit conditions if the presently examined set of exit conditions is satisfied.

46. A programmable sequence controller as defined in claim 44, further comprising:

(E) means for interconnecting the controller to an external data communication device for user programming, monitoring, and debugging the control program.

47. A programmable sequence controller as defined in claim 44, further comprising:

(E) a clock-calendar for communicating with the central processing unit and for generating a number representing time, and wherein the sets of exit conditions may further specify time represented by the clock-calendar as part of the set of exit conditions.

48. A programmable sequence controller defined in claim 44, wherein said control program can specify the condition of drum lines in at least two simulated sequence drums and wherein said central processing unit comprises means for scanning and executing any one line of each drum on a repetitive sequential basis, and wherein the control program can specify the ON or OFF state of addressable internal memory bits and wherein the set of exit conditions for all the drum lines of all the drums can make reference to the ON or OFF state of any internal memory bit as part of its set of exit conditions, the central processing unit further programmed to execute drum lines specifying the turning ON or OFF of internal memory bits and to examine sets of exit conditions specifying the states of selected internal memory bits regardless of where the states for these internal memory bits were set;

thereby allowing the simulated sequence drums to indirectly reference each other via the internal memory bits.

49. A programmable sequence controller as defined in claim 44, wherein said input circuitry incorporates means for examining less than all the inputs from the external device or system during each scan of the simulated sequence drum.

50. A programmable sequence controller for the control of at least one external device or system, the device or system generating inputs to the controller and the controller generating output driver signals for driving said device or system, said controller comprising:

(A) input circuitry communicating with the inputs from the external device or system, and responsive thereto, for generating signals of selected inputs;

(B) output driver circuitry, interconnected to the device or system, for generating output driver signals; and

(C) a central processing unit communicating with the input circuitry and the output driver circuitry, said central processing unit having means for generating addressable internal memory bits and programmed to execute a control program representing the desired states of said output driver signals in relationship to the state of selected inputs generated by the input circuitry and selected addressable internal memory bits, said control program comprising at least two simulated sequence drums, each drum comprising a plurality of addressable drum lines, each drum line defining selected output driver signals as being in selected states as well as selected internal memory bits as being in selected states, and said drum line able to specify a set of exit conditions, each set of exit conditions specifying a drum line to be next executed by the controller, the sets of exit conditions specifying states of specified inputs, specified output driver signals, and specified internal memory bits, the central processing unit further programmed to execute one of the drum lines for each simulated sequence drum during each scan of the simulated sequence drum and further programmed so as to allow drum lines of any particular simulated sequence drum to be able to reference other drum lines of other simulated sequence drums only via the state of selected internal memory bits, and the central processing unit further programmed to examine the set of exit conditions for the presently executed drum line of each simulated drum so as to next execute a drum line specified by the set of exit conditions if these exit conditions are satisfied;

whereby the controller executes a different line of any simulated sequence drum if the exit conditions for the presently executed line for that sequence drum is satisfied and whereby simulated sequence drums may indirectly communicate with each other via the internal memory bits.

51. A programmable sequence controller as defined in claim 50, wherein each drum line specified by each set of exit conditions must be a drum line within the same simulated sequence drum as the presently executed drum line containing the presently examined set of exit conditions.

52. A programmable sequence controller for control of at least one external device or system providing a plurality of input state signals indicative of the state of the device or system, and accepting a plurality of output driver signals which drive said device or system toward desired states, said controller comprising:

(A) means for communicating with the input state signals from the external device or system, and responsive thereto, for generating signals of selected inputs;

(B) means, interconnectable with the device or system, for generating output driver signals; and

(C) means, interconnected to the input communicating means and output driver signal generating means, for simulating and executing at least one sequence drum comprising a plurality of selectable drum lines, each defining,

(a) specified states for specified output driver signals, and

(b) at least two sets of exit conditions, each set of exit conditions specifying a drum line to be next executed, said sets of exit conditions also specifying the states of selected input state signals and output drum signals for satisfying the set of exit conditions, the executing of the simulated sequence drum comprising execution of one of said drum lines by specifying to the output driver signal generating means the states of specified output driver signals and by examining the drum line'"'"'s sets of exit conditions by comparing the desired states of the specified input state signals and output driver signals with the actual states of these respective signals, and causing the drum line specified by the set of exit conditions to be next executed if said set of exit conditions is satisfied.

53. A programmable sequence controller as defined in claim 52, wherein said means for simulating and executing the drum sequentially examines the sets of exit conditions for the presently executed drum line and terminates said examination when a set of exit conditions is satisfied or when all the sets of exit conditions are not satisfied.

54. The programmable sequence controller defined in claim 52, further comprising a clock for providing input time state signals, wherein said time state signals can be specified in any set of exit conditions, and wherein said means for simulating and executing the drum further comprises means for examining said specified time state signals by comparing the specified time states with the state signals generated by the clock.

55. The programmable sequence controller as defined in claim 52 wherein said input state signals include analog signals and said simulating and executing means is provided at least in part by a digital computer;

said programmable sequence controller further comprising;

(D) an analog to digital converter for converting analog state input signals to digital state signals for said digital computer.

56. A programmable sequence controller for control of at least one external device or system providing a plurality of input state signals indicative of the state of the device or system, and accepting a plurality of output driver signals which drive said device or system toward desired states, said controller comprising:

(A) a digital computer having an executive program stored therein for simulating and executing at least one sequence drum comprising a plurality of selectable drum lines, each capable of defining,

(1) specified states for specified output driver signals, and

(2) at least two sets of exit conditions, each set of exit conditions specifying a drum line to be next executed, said sets of exit conditions also specifying the states of selected input state signals and output driver signals for satisfying the set of exit conditions, the executive program of the digital computer causing the digital computer to execute one of said drum lines and to examine the drum line'"'"'s sets of exit conditions by comparing the desired states of the specified input state signals and output driver signals with the actual states of these respective signals, and for causing the drum line specified by the set of exit conditions to be next executed if said set of exit conditions is satisfied; and

(B) means, communicating with the digital computer, for user defining the selectable drum lines, and for monitoring these drum lines as well as the operation of the programmable sequence controller.

57. The method of operating a control system for control of at least one external device or system providing a plurality of input state signals indicative of the state of the device or system and accepting a plurality of output driver signals which drive said device or system towards desired states, said method comprising:

(A) simulating at least one sequence drum comprising a plurality of selectable drum lines, each defining,

(a) specified states for specified output driver signals, and

(b) at least two sets of exit conditions, each set of exit conditions specifying a drum line to be next executed, said sets of exit conditions also specifying the states of selected input state signals and output driver signals for satisfying the set of exit conditions; and

(B) executing one of said drum lines and examining its sets of exit conditions by comparing the desired states of the specified input state signals and output driver signals with the actual states of these respective signals, and causing the drum lines specified by the set of exit conditions to be next executed if said set of exit conditions is satisfied.